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[40.133.238.146]) by smtp.gmail.com with ESMTPSA id s10-20020a65690a000000b0051b0e564963sm1320291pgq.49.2023.04.10.18.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 18:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681175186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wpL42c9J2QGyr3Q5COzWKJRPwuGzBbj68w1re0qrOug=; b=IMTLNXjVdG+a8pDuh/CK1ugU+lZsI/H2UJn/qrRMxdqvKlNRTeViDlP6iRdOAE4ELE Px4+2AQ+BsT2qp/jgtETh60TPy7sxHPwYKeRZqjM/k1oj1g0C2L0mX3LTstsVWeDUFO0 a0fnoXvG8w70KYD82D1H9JGoL6ZgVobIufsn/f+QTSRCbE5VPN47p4ZwsQ0esP4WzwF6 +QkSTHcaW/pQ83Rcf5JVlS7o1aVbHfpLUH+03Ur5rXxpUHx7tCDNa/uTOSa1evvQYceN QWphzgFwDHm4EqNLq1uLG1I0uUYCsU1HUuRWazXt0HFcEvYfs65oiHbVo9la0BR6dWqP QB5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681175186; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wpL42c9J2QGyr3Q5COzWKJRPwuGzBbj68w1re0qrOug=; b=zw/e2Rdgh9FBFWcYYidD+HVei8a4WRfW9qUTGdGKqrUmur2mYRMj/sji47MiJL3I4j oMxLKJEg/0zUv/yN9UJsF572+4WGGYKzAJHtfMLiQsIvSX0WzZHBvstrc43ApsVY7BX6 4LmPT3K0sY1FkcelYmnzN5i2e024xzZU2AELmHVdVGhvOfT30HXoSkUt4gXEEWJRkS18 s5meicqYm3rn3iA1xlluugfYa4WfNwF7WO1kNtmI2o/QSnVf5nf5Zwo3lLVt2XoYek72 OUypjjUiEjIwg5ygrgD3mtYoodR/+NtVnfXS16BoIGE0Urti9vCmxdFvWGCLo/PhptR6 PMgw== X-Gm-Message-State: AAQBX9faFx+MNzTDbQ62OJ5Mc0xulZsrXe4/Fqeh2uNA3tuzWB4orucb kck5z/9Cq1meXzfvGt1dOAVv00x1LlUzK5XECOvJ4g== X-Google-Smtp-Source: AKy350aZBlDuuG0OSSzi/IOhXKZ5f02Xg1og2/6i/TWk+kVbyUe5NaZnk4HqNZi2L/HGKgnvj8reEw== X-Received: by 2002:a17:90b:164f:b0:240:67d5:aea1 with SMTP id il15-20020a17090b164f00b0024067d5aea1mr16790701pjb.14.1681175186315; Mon, 10 Apr 2023 18:06:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Date: Mon, 10 Apr 2023 18:04:43 -0700 Message-Id: <20230411010512.5375-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org> References: <20230411010512.5375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1681175499921100001 Content-Type: text/plain; charset="utf-8" Interpret the variable argument placement in the caller. Mark the argument register const, because they must be passed to add_qemu_ldst_label unmodified. This requires a bit of local variable renaming, because addrlo was being modified. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tcg/ppc/tcg-target.c.inc | 164 +++++++++++++++++++++------------------ 1 file changed, 89 insertions(+), 75 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 77abb7d20c..90093a6509 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2118,7 +2118,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp o= pc, /* Record the context of a call to the out of line helper code for the slow path for a load or store, so that we can later generate the correct helper code. */ -static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, +static void add_qemu_ldst_label(TCGContext *s, bool is_ld, + TCGType type, MemOpIdx oi, TCGReg datalo_reg, TCGReg datahi_reg, TCGReg addrlo_reg, TCGReg addrhi_reg, tcg_insn_unit *raddr, tcg_insn_unit *lptr) @@ -2126,6 +2127,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, MemOpIdx oi, TCGLabelQemuLdst *label =3D new_ldst_label(s); =20 label->is_ld =3D is_ld; + label->type =3D type; label->oi =3D oi; label->datalo_reg =3D datalo_reg; label->datahi_reg =3D datahi_reg; @@ -2288,30 +2290,19 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 #endif /* SOFTMMU */ =20 -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_ld(TCGContext *s, + const TCGReg datalo, const TCGReg datahi, + const TCGReg addrlo, const TCGReg addrhi, + const MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase, index; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); + index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), tru= e); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2319,80 +2310,71 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); } rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo =3D TCG_REG_TMP1; + index =3D TCG_REG_TMP1; + } else { + index =3D addrlo; } #endif =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, rbase, index)); tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0)); } else if (rbase !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4)); + tcg_out32(s, LWZX | TAB(datahi, rbase, index)); tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0)); - } else if (addrlo =3D=3D datahi) { - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); + } else if (index =3D=3D datahi) { + tcg_out32(s, LWZ | TAI(datalo, index, 4)); + tcg_out32(s, LWZ | TAI(datahi, index, 0)); } else { - tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); - tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); + tcg_out32(s, LWZ | TAI(datahi, index, 0)); + tcg_out32(s, LWZ | TAI(datalo, index, 4)); } } else { uint32_t insn =3D qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; if (!have_isa_2_06 && insn =3D=3D LDBRX) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4)); + tcg_out32(s, LWBRX | TAB(datalo, rbase, index)); tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); } else if (insn) { - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | TAB(datalo, rbase, index)); } else { insn =3D qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; - tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | TAB(datalo, rbase, index)); tcg_out_movext(s, TCG_TYPE_REG, datalo, TCG_TYPE_REG, opc & MO_SSIZE, datalo); } } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +static void tcg_out_qemu_st(TCGContext *s, + const TCGReg datalo, const TCGReg datahi, + const TCGReg addrlo, const TCGReg addrhi, + const MemOpIdx oi, TCGType data_type) { - TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); - MemOpIdx oi; - MemOp opc, s_bits; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; + TCGReg rbase, index; + #ifdef CONFIG_SOFTMMU - int mem_index; tcg_insn_unit *label_ptr; -#else - unsigned a_bits; -#endif =20 - datalo =3D *args++; - datahi =3D (TCG_TARGET_REG_BITS =3D=3D 32 && is_64 ? *args++ : 0); - addrlo =3D *args++; - addrhi =3D (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); - oi =3D *args++; - opc =3D get_memop(oi); - s_bits =3D opc & MO_SIZE; - -#ifdef CONFIG_SOFTMMU - mem_index =3D get_mmuidx(oi); - addrlo =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); + index =3D tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), fal= se); =20 /* Load a pointer into the current opcode w/conditional branch-link. */ label_ptr =3D s->code_ptr; @@ -2400,45 +2382,47 @@ static void tcg_out_qemu_st(TCGContext *s, const TC= GArg *args, bool is_64) =20 rbase =3D TCG_REG_R3; #else /* !CONFIG_SOFTMMU */ - a_bits =3D get_alignment_bits(opc); + unsigned a_bits =3D get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); } rbase =3D guest_base ? TCG_GUEST_BASE_REG : 0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); - addrlo =3D TCG_REG_TMP1; + index =3D TCG_REG_TMP1; + } else { + index =3D addrlo; } #endif =20 if (TCG_TARGET_REG_BITS =3D=3D 32 && s_bits =3D=3D MO_64) { if (opc & MO_BSWAP) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4)); + tcg_out32(s, STWBRX | SAB(datalo, rbase, index)); tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0)); } else if (rbase !=3D 0) { - tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); - tcg_out32(s, STWX | SAB(datahi, rbase, addrlo)); + tcg_out32(s, ADDI | TAI(TCG_REG_R0, index, 4)); + tcg_out32(s, STWX | SAB(datahi, rbase, index)); tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0)); } else { - tcg_out32(s, STW | TAI(datahi, addrlo, 0)); - tcg_out32(s, STW | TAI(datalo, addrlo, 4)); + tcg_out32(s, STW | TAI(datahi, index, 0)); + tcg_out32(s, STW | TAI(datalo, index, 4)); } } else { uint32_t insn =3D qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; if (!have_isa_2_06 && insn =3D=3D STDBRX) { - tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); + tcg_out32(s, STWBRX | SAB(datalo, rbase, index)); + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, index, 4)); tcg_out_shri64(s, TCG_REG_R0, datalo, 32); tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1)); } else { - tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); + tcg_out32(s, insn | SAB(datalo, rbase, index)); } } =20 #ifdef CONFIG_SOFTMMU - add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, - s->code_ptr, label_ptr); + add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, + addrlo, addrhi, s->code_ptr, label_ptr); #endif } =20 @@ -2972,16 +2956,46 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; =20 case INDEX_op_qemu_ld_i32: - tcg_out_qemu_ld(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_ld_i64: - tcg_out_qemu_ld(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_ld(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; case INDEX_op_qemu_st_i32: - tcg_out_qemu_st(s, args, false); + if (TCG_TARGET_REG_BITS >=3D TARGET_LONG_BITS) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I32); + } else { + tcg_out_qemu_st(s, args[0], -1, args[1], args[2], + args[3], TCG_TYPE_I32); + } break; case INDEX_op_qemu_st_i64: - tcg_out_qemu_st(s, args, true); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + tcg_out_qemu_st(s, args[0], -1, args[1], -1, + args[2], TCG_TYPE_I64); + } else if (TARGET_LONG_BITS =3D=3D 32) { + tcg_out_qemu_st(s, args[0], args[1], args[2], -1, + args[3], TCG_TYPE_I64); + } else { + tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], + args[4], TCG_TYPE_I64); + } break; =20 case INDEX_op_setcond_i32: --=20 2.34.1