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[82.135.86.174]) by smtp.googlemail.com with ESMTPSA id n19-20020a509353000000b005002daeb27asm5129282eda.37.2023.04.10.10.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 10:50:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681149001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+jb7ryK3VqNFA6tSClMkrHqVatLxl4Q4pq+0cLxYBnE=; b=UY1bwBVCiYGrYghyvhWAehzZwQJuus/k0UZUeq1xIRQ/D+AlTDMqPOsdasmr4g76wd oFqvLq1feV9zvRfGjn7rG1ZK+T64PAP/Rn3eN+ODddWqh05jjsLjZTIo01GM2stJxU+H hBJKwnE/iX/JRYhBIJqglj9+0JC0my5zUADKrXDu3AYEmF1/LGtx4WkhEKgOq49OfOhR DXvvCiTFIlOvfHgt3/n/S/k8Gs7pc9kp2SbvguU0K/Jn4b7Z67akUqUTWpLvfjIf5Zsx lc4AV0uDfQdU2lOjeFfxTcgH07ex6izf8XSTRhno8ueDGJNCjp08jQUMYIH1yiP13OGi d8Pg== X-Gm-Message-State: AAQBX9ek/1iGrygGT6ZzA4w8RxVU1EsXaKGBeEnz8u3+SG38j+hfiJ3p qcb7DEi/UbuU1OLyLiYYxhXMUmfsxGy0RvrP X-Google-Smtp-Source: AKy350bZEa02IOdciH9+aarhLZxjB3NuvC4A0hD0Ks+8brjtkRE9NFB4T0I2KnbaSllmLFfExQfisQ== X-Received: by 2002:aa7:d8c7:0:b0:504:91ca:5da3 with SMTP id k7-20020aa7d8c7000000b0050491ca5da3mr5883158eds.22.1681149000907; Mon, 10 Apr 2023 10:50:00 -0700 (PDT) From: Johannes Thumshirn To: qemu-devel@nongnu.org Cc: Alistair Francis , Javier Rodriguez , =?UTF-8?q?Jorge=20Sanjuan=20Garc=C3=ADa?= , Peter Maydell , Dmitry Fomichev , Johannes Thumshirn Subject: [PATCH v3 2/4] Add MEN Chameleon Bus via PCI carrier Date: Mon, 10 Apr 2023 19:49:08 +0200 Message-Id: <20230410174910.4806-3-jth@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230410174910.4806-1-jth@kernel.org> References: <20230410174910.4806-1-jth@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.85.208.50; envelope-from=morbidrsa@gmail.com; helo=mail-ed1-f50.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1681149080902100001 Content-Type: text/plain; charset="utf-8" Add PCI based MEN Chameleon Bus carrier emulation. Signed-off-by: Johannes Thumshirn Acked-by: Alistair Francis --- hw/mcb/Kconfig | 6 + hw/mcb/mcb-pci.c | 297 ++++++++++++++++++++++++++++++++++++++++++++ hw/mcb/meson.build | 1 + hw/mcb/trace-events | 3 + hw/mcb/trace.h | 1 + meson.build | 1 + 6 files changed, 309 insertions(+) create mode 100644 hw/mcb/mcb-pci.c create mode 100644 hw/mcb/trace-events create mode 100644 hw/mcb/trace.h diff --git a/hw/mcb/Kconfig b/hw/mcb/Kconfig index 36a7a583a8..7deb96c2fe 100644 --- a/hw/mcb/Kconfig +++ b/hw/mcb/Kconfig @@ -1,2 +1,8 @@ config MCB bool + +config MCB_PCI + bool + default y if PCI_DEVICES + depends on PCI + select MCB diff --git a/hw/mcb/mcb-pci.c b/hw/mcb/mcb-pci.c new file mode 100644 index 0000000000..516f133c2e --- /dev/null +++ b/hw/mcb/mcb-pci.c @@ -0,0 +1,297 @@ +/* + * QEMU MEN Chameleon Bus emulation + * + * Copyright (C) 2023 Johannes Thumshirn + * + * This code is licensed under the GPL version 2 or later. See the + * COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/mcb/mcb.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_device.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "trace.h" + +typedef struct { + uint8_t revision; + char model; + uint8_t minor; + uint8_t bus_type; + uint16_t magic; + uint16_t reserved; + /* This one has no '\0' at the end!!! */ + char filename[12]; +} ChameleonFPGAHeader; +#define CHAMELEON_BUS_TYPE_WISHBONE 0 +#define CHAMELEONV2_MAGIC 0xabce + +typedef struct { + PCIDevice dev; + MCBus bus; + MemoryRegion ctbl; + uint16_t status; + uint8_t int_set; + ChameleonFPGAHeader *header; + + uint8_t minor; + uint8_t rev; + uint8_t model; +} MPCIState; + +#define TYPE_MCB_PCI "mcb-pci" + +#define MPCI(obj) \ + OBJECT_CHECK(MPCIState, (obj), TYPE_MCB_PCI) + +#define CHAMELEON_TABLE_SIZE 0x200 +#define N_MODULES 32 + +#define PCI_VENDOR_ID_MEN 0x1a88 +#define PCI_DEVICE_ID_MEN_MCBPCI 0x4d45 + +static uint32_t read_header(MPCIState *s, hwaddr addr) +{ + uint32_t ret =3D 0; + ChameleonFPGAHeader *header =3D s->header; + + switch (addr >> 2) { + case 0: + ret |=3D header->revision; + ret |=3D header->model << 8; + ret |=3D header->minor << 16; + ret |=3D header->bus_type << 24; + break; + case 1: + ret |=3D header->magic; + ret |=3D header->reserved << 16; + break; + case 2: + memcpy(&ret, header->filename, sizeof(uint32_t)); + break; + case 3: + memcpy(&ret, header->filename + sizeof(uint32_t), + sizeof(uint32_t)); + break; + case 4: + memcpy(&ret, header->filename + 2 * sizeof(uint32_t), + sizeof(uint32_t)); + } + + return ret; +} + +static uint32_t read_gdd(MCBDevice *mdev, int reg) +{ + ChameleonDeviceDescriptor *gdd; + uint32_t ret =3D 0; + + gdd =3D mdev->gdd; + + switch (reg) { + case 0: + ret =3D gdd->reg1; + break; + case 1: + ret =3D gdd->reg2; + break; + case 2: + ret =3D gdd->offset; + break; + case 3: + ret =3D gdd->size; + break; + } + + return ret; +} + +static uint64_t mpci_chamtbl_read(void *opaque, hwaddr addr, unsigned size) +{ + MPCIState *s =3D opaque; + MCBus *bus =3D &s->bus; + MCBDevice *mdev; + + trace_mpci_chamtbl_read(addr, size); + + if (addr < sizeof(ChameleonFPGAHeader)) { + return le32_to_cpu(read_header(s, addr)); + } else if (addr >=3D sizeof(ChameleonFPGAHeader) && + addr < CHAMELEON_TABLE_SIZE) { + /* Handle read on chameleon table */ + BusChild *kid; + DeviceState *qdev; + int slot; + int offset; + int i; + + offset =3D addr - sizeof(ChameleonFPGAHeader); + slot =3D offset / sizeof(ChameleonDeviceDescriptor); + + kid =3D QTAILQ_FIRST(&BUS(bus)->children); + for (i =3D 0; i < slot; i++) { + kid =3D QTAILQ_NEXT(kid, sibling); + if (!kid) { /* Last element */ + return ~0U; + } + } + qdev =3D kid->child; + mdev =3D MCB_DEVICE(qdev); + offset -=3D slot * 16; + + return le32_to_cpu(read_gdd(mdev, offset / 4)); + } + + return 0; +} + +static void mpci_chamtbl_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + + if (addr < CHAMELEON_TABLE_SIZE) { + trace_mpci_chamtbl_write(addr, val); + } + + return; +} + +static const MemoryRegionOps mpci_chamtbl_ops =3D { + .read =3D mpci_chamtbl_read, + .write =3D mpci_chamtbl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + }, +}; + +static void mcb_pci_set_irq(void *opaque, int intno, int level) +{ + MCBDevice *mdev =3D opaque; + MCBus *bus =3D MCB_BUS(qdev_get_parent_bus(DEVICE(mdev))); + PCIDevice *pcidev =3D PCI_DEVICE(BUS(bus)->parent); + MPCIState *dev =3D MPCI(pcidev); + + if (level) { + pci_set_irq(&dev->dev, !dev->int_set); + pci_set_irq(&dev->dev, dev->int_set); + } else { + uint16_t level_status =3D dev->status; + + if (level_status && !dev->int_set) { + pci_irq_assert(&dev->dev); + dev->int_set =3D 1; + } else if (!level_status && dev->int_set) { + pci_irq_deassert(&dev->dev); + dev->int_set =3D 0; + } + } +} + +static void mcb_pci_write_config(PCIDevice *pci_dev, uint32_t address, + uint32_t val, int len) +{ + pci_default_write_config(pci_dev, address, val, len); +} + +static void mcb_pci_realize(PCIDevice *pci_dev, Error **errp) +{ + MPCIState *s =3D MPCI(pci_dev); + uint8_t *pci_conf =3D s->dev.config; + ChameleonFPGAHeader *header; + MCBus *bus =3D &s->bus; + + header =3D g_new0(ChameleonFPGAHeader, 1); + + s->header =3D header; + + header->revision =3D s->rev; + header->model =3D (char) s->model; + header->minor =3D s->minor; + header->bus_type =3D CHAMELEON_BUS_TYPE_WISHBONE; + header->magic =3D CHAMELEONV2_MAGIC; + memcpy(&header->filename, "QEMU MCB PCI", 12); + + pci_dev->config_write =3D mcb_pci_write_config; + pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */ + pci_conf[PCI_COMMAND] =3D PCI_COMMAND_MEMORY; + + mcb_bus_init(bus, sizeof(MCBus), DEVICE(pci_dev), N_MODULES, + mcb_pci_set_irq); + + memory_region_init(&bus->mmio_region, OBJECT(s), "mcb-pci.mmio", + 2048 * 1024); + memory_region_init_io(&s->ctbl, OBJECT(s), &mpci_chamtbl_ops, + s, "mpci_chamtbl_ops", CHAMELEON_TABLE_SIZE); + memory_region_add_subregion(&bus->mmio_region, 0, &s->ctbl); + pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, + &bus->mmio_region); + +} + +static void mcb_pci_unrealize(PCIDevice *pci_dev) +{ + MPCIState *s =3D MPCI(pci_dev); + + g_free(s->header); + s->header =3D NULL; +} + +static const VMStateDescription vmstate_mcb_pci =3D { + .name =3D "mcb-pci", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(dev, MPCIState), + VMSTATE_END_OF_LIST() + } +}; + +static Property mcb_pci_props[] =3D { + DEFINE_PROP_UINT8("revision", MPCIState, rev, 1), + DEFINE_PROP_UINT8("minor", MPCIState, minor, 0), + DEFINE_PROP_UINT8("model", MPCIState, model, 0x41), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mcb_pci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->realize =3D mcb_pci_realize; + k->exit =3D mcb_pci_unrealize; + k->vendor_id =3D PCI_VENDOR_ID_MEN; + k->device_id =3D PCI_DEVICE_ID_MEN_MCBPCI; + k->class_id =3D PCI_CLASS_BRIDGE_OTHER; + + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "MEN Chameleon Bus over PCI"; + dc->vmsd =3D &vmstate_mcb_pci; + device_class_set_props(dc, mcb_pci_props); +} + +static const TypeInfo mcb_pci_info =3D { + .name =3D TYPE_MCB_PCI, + .parent =3D TYPE_PCI_DEVICE, + .instance_size =3D sizeof(MPCIState), + .class_init =3D mcb_pci_class_init, + .interfaces =3D (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { } + }, +}; + +static void mcb_pci_register_types(void) +{ + type_register(&mcb_pci_info); +} +type_init(mcb_pci_register_types); diff --git a/hw/mcb/meson.build b/hw/mcb/meson.build index a385edc07c..4e1a0f0cdb 100644 --- a/hw/mcb/meson.build +++ b/hw/mcb/meson.build @@ -1 +1,2 @@ softmmu_ss.add(when: 'CONFIG_MCB', if_true: files('mcb.c')) +softmmu_ss.add(when: 'CONFIG_MCB_PCI', if_true: files('mcb-pci.c')) diff --git a/hw/mcb/trace-events b/hw/mcb/trace-events new file mode 100644 index 0000000000..e1adf9c8e3 --- /dev/null +++ b/hw/mcb/trace-events @@ -0,0 +1,3 @@ +# mcb-pci.c +mpci_chamtbl_read(unsigned long addr, unsigned int size) "read from addres= s 0x%lx size %d" +mpci_chamtbl_write(unsigned long addr, uint64_t val) "invalid write to 0x%= lx: 0x%" PRIx64 diff --git a/hw/mcb/trace.h b/hw/mcb/trace.h new file mode 100644 index 0000000000..35653b3381 --- /dev/null +++ b/hw/mcb/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_mcb.h" diff --git a/meson.build b/meson.build index 29f8644d6d..ff8305440b 100644 --- a/meson.build +++ b/meson.build @@ -2986,6 +2986,7 @@ if have_system 'hw/input', 'hw/intc', 'hw/isa', + 'hw/mcb', 'hw/mem', 'hw/mips', 'hw/misc', --=20 2.39.2