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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 2/2] target/arm: Copy guarded bit in combine_cacheattrs
Date: Mon, 10 Apr 2023 15:14:08 +0100
Message-Id: <20230410141408.3564269-3-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
The guarded bit comes from the stage1 walk.
Fixes: Coverity CID 1507929
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 58a6de09bc9..6d72950a795 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2576,6 +2576,7 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
=20
assert(!s1.is_s2_format);
ret.is_s2_format =3D false;
+ ret.guarded =3D s1.guarded;
=20
if (s1.attrs =3D=3D 0xf0) {
tagged =3D true;
--=20
2.34.1