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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 1/2] target/arm: PTE bit GP only applies to stage1
Date: Mon, 10 Apr 2023 15:14:07 +0100
Message-Id: <20230410141408.3564269-2-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Only perform the extract of GP during the stage1 walk.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index ec3f51782aa..58a6de09bc9 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1585,11 +1585,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T=
ranslate *ptw,
result->f.attrs.secure =3D false;
}
=20
- /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. =
*/
- if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
- result->f.guarded =3D extract64(attrs, 50, 1); /* GP */
- }
-
if (regime_is_stage2(mmu_idx)) {
result->cacheattrs.is_s2_format =3D true;
result->cacheattrs.attrs =3D extract32(attrs, 2, 4);
@@ -1600,6 +1595,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T=
ranslate *ptw,
assert(attrindx <=3D 7);
result->cacheattrs.is_s2_format =3D false;
result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8);
+
+ /* When in aarch64 mode, and BTI is enabled, remember GP in the TL=
B. */
+ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) {
+ result->f.guarded =3D extract64(attrs, 50, 1); /* GP */
+ }
}
=20
/*
--=20
2.34.1