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([2602:ae:1541:f901:8bb4:5a9d:7ab7:b4b8]) by smtp.gmail.com with ESMTPSA id d9-20020a170902c18900b0019d397b0f18sm3530780pld.214.2023.04.07.19.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Apr 2023 19:43:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680921826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZD8D6s1mTsZ3Wn5qEWwRrv84r6pcuNTBrq2RsXDvc+c=; b=W/91gidsjvoXEE+rAUGpm233QgUDJr99+R+jskgo5ZQc93gfApAewQRXLZK6LDTdYk qpDE5rxsVYuutImUDTZRYZ/o7gK0OEPFp+/435LDZ41sArWVpEu1zPFaJZPnbVFTFYFT DvWTgZYAgOzT2BgU99KSbI9pxil002qQ2AyZL9UnGgmweR3O2jnYx93g6KtNVadY7rNi EFLhbqWwWlZ2DLsrz+VgEHjKpl/J3jGG/J+dE75S8EZoiyYX0oSYRbJF6zftRneVkwnN hGSlHckhALxBhBpNxdutE0jfpw6NOCMcHAQXx/0GQ951cqG5ZJPrltXFkj5URMcXUpys +Ozw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680921827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZD8D6s1mTsZ3Wn5qEWwRrv84r6pcuNTBrq2RsXDvc+c=; b=WMlyek5g4mMqm8M7u/vVV6Ot1/J6hiNDaomkTPf1+QWgoOVe7mTYc2IluIp8jkWyrR UO19gtdhAn/I7tz0dgG4che9IebxjlAcjoqKMe8kWcHk/qGjb4fa/qhWvtPFcWeuDRXd 1E2HWelhu1CPE4LkIejlqBUhSOjSoHX4/z+23gKVT5whJguuBzzytRO8FuPXA6DeKHIA uZxOOnEGXxQawLB0ku0yZ1J+Y9P7qkLTxuq/0JId3ifVhUaypMb9tM3iuwWEakuP/9IE Mm2NtFPTKXlsP2UD1t29W0eqpYsZtv59epcOqmE9IggswX+puFY1BImBegzzOOw7tTei aPJw== X-Gm-Message-State: AAQBX9fOR/D9VNa2tHnmC4gU7ZciRV6eBN8lLw4Fg7WAq0RzSgUKzrUt uEMtJV39bqQo2TNdx6G0XlhpW8Jusn5OXt8mtjs= X-Google-Smtp-Source: AKy350bYNHVDZn72PaAGNatHFRmz0FB36y1WlIRW+4D9NPfII8ivn04GS/qcb0kKAm97FO8mKykzUQ== X-Received: by 2002:a17:903:2281:b0:1a1:b15a:d916 with SMTP id b1-20020a170903228100b001a1b15ad916mr6006834plh.3.1680921826681; Fri, 07 Apr 2023 19:43:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH 34/42] tcg/mips: Simplify constraints on qemu_ld/st Date: Fri, 7 Apr 2023 19:43:06 -0700 Message-Id: <20230408024314.3357414-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408024314.3357414-1-richard.henderson@linaro.org> References: <20230408024314.3357414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1680922041752100003 Content-Type: text/plain; charset="utf-8" The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 13 +++++-------- tcg/mips/tcg-target-con-str.h | 2 -- tcg/mips/tcg-target.c.inc | 30 ++++++++---------------------- 3 files changed, 13 insertions(+), 32 deletions(-) diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h index fe3e868a2f..864034f468 100644 --- a/tcg/mips/tcg-target-con-set.h +++ b/tcg/mips/tcg-target-con-set.h @@ -12,15 +12,13 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) -C_O0_I2(SZ, S) -C_O0_I3(SZ, S, S) -C_O0_I3(SZ, SZ, S) +C_O0_I3(rZ, r, r) +C_O0_I3(rZ, rZ, r) C_O0_I4(rZ, rZ, rZ, rZ) -C_O0_I4(SZ, SZ, S, S) -C_O1_I1(r, L) +C_O0_I4(rZ, rZ, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, r, rIK) @@ -30,7 +28,6 @@ C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_O1_I4(r, rZ, rZ, rZ, 0) C_O1_I4(r, rZ, rZ, rZ, rZ) -C_O2_I1(r, r, L) -C_O2_I2(r, r, L, L) +C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, rZ, rZ, rN, rN) diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h index e4b2965c72..413c280a7a 100644 --- a/tcg/mips/tcg-target-con-str.h +++ b/tcg/mips/tcg-target-con-str.h @@ -9,8 +9,6 @@ * REGS(letter, register_mask) */ REGS('r', ALL_GENERAL_REGS) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) =20 /* * Define constraint letters for constants: diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 16b9d09959..34908c799a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -176,20 +176,6 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, #define TCG_CT_CONST_WSZ 0x2000 /* word size */ =20 #define ALL_GENERAL_REGS 0xffffffffu -#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) - -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) -#define ALL_QSTORE_REGS \ - (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ - ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ - : (1 << TCG_REG_A1))) -#else -#define ALL_QLOAD_REGS NOA0_REGS -#define ALL_QSTORE_REGS NOA0_REGS -#endif - =20 static bool is_p2m1(tcg_target_long val) { @@ -2488,18 +2474,18 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGO= pcode op) =20 case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) : C_O1_I2(r, r, r)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS =3D=3D 64 || TARGET_LONG_BITS =3D=3D 32 - ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); + ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, L) - : C_O2_I2(r, r, L, L)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(SZ, S) - : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(SZ, SZ, S) - : C_O0_I4(SZ, SZ, S, S)); + return (TCG_TARGET_REG_BITS =3D=3D 64 ? C_O0_I2(rZ, r) + : TARGET_LONG_BITS =3D=3D 32 ? C_O0_I3(rZ, rZ, r) + : C_O0_I4(rZ, rZ, r, r)); =20 default: g_assert_not_reached(); --=20 2.34.1