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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w4z24gtDXDugF/zsUCpawt2hpra7MWomBPWmPIVOu3U=; b=o7RCUMljqcUNkavvT5acNcbWGWpzDnYaGnNm6/DGFmJA9UC9o4r0mY39+D59liDzXb VBsyY8fM2lVES4nuzhFb0L0XSez+84FMKWY3svTwIvOFmQh+u8OeGBuwHd7LCsnIOeFi 0F82j6HyFI5L6/j/MvQ0JhpDiqLmD6xTYzJk0V24ADefwClNI21HFmeuB53acHisiau9 OXaLBt1iKYbmta+OFK7aVCAgtfo7OMp37/dD4AVp91pawdAnh/OSsJlVcK/+1dTfkVVm FrH1NbRmI3E7zocXFccxkqPOSzeGznZDs7CcRDONEcg2XNdZfHr7XSfuitspXJN9od+Z Sc6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w4z24gtDXDugF/zsUCpawt2hpra7MWomBPWmPIVOu3U=; b=lX6ql19lr5kPwvIRhUdfII87xvnQIFo/hKReVtJo6SHqAQ4iTl6t+tYlK/9QA/pFnU xN/+hcJyRZQQpvY3MatGPQupDKK/67cOwlSY/iMOrgAybg+QdjT8x8JgvvxpTDLeg5jQ 5MUVJbE8edwuf87Ok5exO9Lw3MEuyI/S6kwrcJswRuL5WkKi/oexkgntkaN+qdQX9E9d J/fa5kei9F2X5Gv45hJycGIIGriKlXN0N89uF8Q72oNhtNnLGbu76yer7K/C8MGm1VW6 VRalhOA1fxgJd2yEjoJ5EqvvGqRKwJLMrsw2SSR3/o84AAVBHD+k3xAdTiOWsMpzCDsq 3woA== X-Gm-Message-State: AAQBX9c0h891D5USUIJv/mRM4TPNDF+vDZyEjLr/FXfcZC024+lNX5Nt sqNZnGnOFiwFjbQWM2V2YnDfx9vBuLbjlxefBbc= X-Google-Smtp-Source: AKy350bTilafw94sdVe0NAK2ycTKhU5y2z2ULa8B+xP+oeahKfIECnAdHjzIrG0JaFY7sKpUnkcUyQ== X-Received: by 2002:a05:6870:d189:b0:17a:a7f3:e591 with SMTP id a9-20020a056870d18900b0017aa7f3e591mr91524oac.26.1680804264750; Thu, 06 Apr 2023 11:04:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 08/20] target/riscv: remove cpu->cfg.ext_f Date: Thu, 6 Apr 2023 15:03:39 -0300 Message-Id: <20230406180351.570807-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804384815100001 Content-Type: text/plain; charset="utf-8" Create a new "f" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are replaced with riscv_has_ext(env, RVF). Remove the old "f" property and 'ext_f' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 26 +++++++++++++------------- target/riscv/cpu.h | 1 - 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5bb03e2ee5..715cbca1b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,12 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && riscv_has_ext(env, RVD) && + riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_f =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -861,7 +861,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; } @@ -875,12 +875,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zfhmin =3D true; } =20 - if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; } =20 - if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { error_setg(errp, "D extension requires F extension"); return; } @@ -905,7 +905,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { error_setg(errp, "Zve32f/Zve64f extensions require F extension"); return; } @@ -938,7 +938,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) error_setg(errp, "Zfinx extension requires Zicsr"); return; } - if (cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVF)) { error_setg(errp, "Zfinx cannot be supported together with F extensio= n"); return; @@ -950,14 +950,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) cpu->cfg.ext_zcb =3D true; cpu->cfg.ext_zcmp =3D true; cpu->cfg.ext_zcmt =3D true; - if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } } =20 if (riscv_has_ext(env, RVC)) { cpu->cfg.ext_zca =3D true; - if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } if (riscv_has_ext(env, RVD)) { @@ -970,7 +970,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension requires F extension"); return; } @@ -1160,7 +1160,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } - if (riscv_cpu_cfg(env)->ext_f) { + if (riscv_has_ext(env, RVF)) { ext |=3D RVF; } if (riscv_has_ext(env, RVD)) { @@ -1500,6 +1500,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVC, .enabled =3D true}, {.name =3D "d", .description =3D "Double-precision float point", .misa_bit =3D RVD, .enabled =3D true}, + {.name =3D "f", .description =3D "Single-precision float point", + .misa_bit =3D RVF, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1528,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1646,7 +1647,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index fba5e9a33c..e5680b0709 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,7 +426,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_f; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2