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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B9x0iEmvZZnGbXL5Z/nMToKlOj5c7ZztL5LLqrRttDI=; b=HSYaYqj72PYQurYdg8h3Cw4jrdp9mLmRnDuyUESiqpjihn0fmCPJImoGPCN1FF0L+d 96ivhaQgbGzTelS8mGCWGzyMCJSu0kEdgdF5Lv23wmqmB4beidMvyy6NQRaS+I6772qi u8WmCzMsUlLWbazYsHAG8UYnmwXa2hqKKwaZenyvUDcLi01X8ieGxZSTWLrVxRj143WV KIGnhg95zJNssuLz+wFkjaOII+T37QKYZldKYVYvT8dEYzrcxP5ephGoLylia1s5TEyJ W0ydtauQajgjnMaTuQ1ICQF8ctQqbQnJhnYCCc71+EvU11AA+rSeL+PwZCFdsS3xDJmY +LHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B9x0iEmvZZnGbXL5Z/nMToKlOj5c7ZztL5LLqrRttDI=; b=Zj2SChyrRHDXSL4Ue6wyuwMutt7Lxi5FZg6ZkPMhl2fRr0Rw8UZdsL/9cRJ7jI7FvD ViOo7UDbgyy94BYq9N1HgfEoX33RQ2+Q0IL0UIT3TJ0lLk6dJgOHA1co+nM52QFCLgkw uwJU3CqGRp2oU0D5QsP87Pcm24HkgiMMZx753WJdMPr/p3loO+0r32ZYtVJSWey8iQCT eK1WVJ9XrF6lVd1v9r+qrK6WN97Y3rJDZ7qwXiZI1lfP/+LCBYBRRpo9DhyVlUf9kLd/ WQD4v0Tvth6DCFLRMBjE2xTj0okU6C+cABI91ZSQ4R8LnpkJ3BBKpDPiGt7xnwEEsnWO LIqg== X-Gm-Message-State: AAQBX9eToKa7g/Th0CjdQBjgbYiNfG91LY830HW6/GfN4eMtt0TXyQTQ XkpzUoNeJ6VrFtAKE6HARi9LXbm+510zHs6bHzA= X-Google-Smtp-Source: AKy350a9oJARNDAXB6dNJKIcFrGpxSsjMXGzsmmS45gnhD/WOhR9oYDqVVv3XthPM27e+wi8Wf6jAA== X-Received: by 2002:a05:6870:b619:b0:183:e8b2:92f6 with SMTP id cm25-20020a056870b61900b00183e8b292f6mr94474oab.27.1680804261483; Thu, 06 Apr 2023 11:04:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 07/20] target/riscv: remove cpu->cfg.ext_d Date: Thu, 6 Apr 2023 15:03:38 -0300 Message-Id: <20230406180351.570807-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804498806100003 Content-Type: text/plain; charset="utf-8" Create a new "d" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are replaced with riscv_has_ext(env, RVD). Remove the old "d" property and 'ext_d' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 17 ++++++++--------- target/riscv/cpu.h | 1 - 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2e00b8f20a..5bb03e2ee5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && riscv_has_ext(env, RVA) && - cpu->cfg.ext_f && cpu->cfg.ext_d && + cpu->cfg.ext_f && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -881,7 +880,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) { error_setg(errp, "D extension requires F extension"); return; } @@ -901,7 +900,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_zve32f =3D true; } =20 - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { error_setg(errp, "Zve64d/V extensions require D extension"); return; } @@ -961,7 +960,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) if (cpu->cfg.ext_f && env->misa_mxl_max =3D=3D MXL_RV32) { cpu->cfg.ext_zcf =3D true; } - if (cpu->cfg.ext_d) { + if (riscv_has_ext(env, RVD)) { cpu->cfg.ext_zcd =3D true; } } @@ -976,7 +975,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { error_setg(errp, "Zcd extension requires D extension"); return; } @@ -1164,7 +1163,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_f) { ext |=3D RVF; } - if (riscv_cpu_cfg(env)->ext_d) { + if (riscv_has_ext(env, RVD)) { ext |=3D RVD; } if (riscv_has_ext(env, RVC)) { @@ -1499,6 +1498,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVA, .enabled =3D true}, {.name =3D "c", .description =3D "Compressed instructions", .misa_bit =3D RVC, .enabled =3D true}, + {.name =3D "d", .description =3D "Double-precision float point", + .misa_bit =3D RVD, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1526,7 +1527,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), - DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_f =3D misa_ext & RVF; - cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9a3847329c..fba5e9a33c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -427,7 +427,6 @@ struct RISCVCPUConfig { bool ext_g; bool ext_m; bool ext_f; - bool ext_d; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2