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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2W7bGVL35Yc0UFJ+sEGELn4vLTKReJQVA0yDUn5MBBM=; b=SMHpaWSFqtU91jTW6Cl0C/3keH5J8sTNOlKTldTOCG+iIMLpAE+7IbisP6VHx2LRwb vZKc/xeDoNTP6HsF1FSdDx+3PVIv0rYZE9rI+fBqfJq/W5ihh2rlhHRtyGxy4T66oP9n XkRZTFwlBfMHJD6s9uRxOAU6G7MtECJzXIE5s7QCQaMSPs98e08cv81vnJq+DZUVAtQ8 GMTrRa0PVO/nK5A/cruIlR7TqqyOqVNaT9RXi7MUjxGCG2iluaXtoOxRuOjL+IiZ/Pl0 kI/XJ69JNzqd+dh9A7PFPsh8Epr7e53a2XsX4DL7xgM3YjvWc0ajG7lRVcWknrcuwl6l Jv8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2W7bGVL35Yc0UFJ+sEGELn4vLTKReJQVA0yDUn5MBBM=; b=oqTigdPsVMQVARU2TAVZ/OyE5E/zjxWySpp2fTgqG+ZX9ax8UkXpIsmrSwRL/Thcdt /lp/8MP2eFAZDS1Py1cUjFSBvQccOItcAOUIya8siGeHIQf/6NWH4j9IeoULlmf37TfD g27MB31catBMOHu9sMyUGUPgPjeasiNJAZGq2K3NLU9QfmXsTa05iFLlnrKBxSs/6IbT Ae5NJb4lbbez3+Do0FrW+J+8ftIGyL3EWHxrqTr0barIYJAsHLxlohk1aM86SgVe+4wn NivbKk9q4JbFna3HMswPj+4qAA2uZGrZh7/lVzX+dFUQxVsGYrkzG6aQ+RqmolDsozXN 5ovw== X-Gm-Message-State: AAQBX9dPwDmiamr6c6e5cAKJEneaF8vCyUaiaPRPurfqqnSJh5VgtoOK X8lwTVJgwNTKPDMuLbmMHFaiup5IeGnMdywewUo= X-Google-Smtp-Source: AKy350ZIvOyYqFqw03bZ15Nan5w7+1SyMWfxL3XFP9qdyPey6THgp/j8Pzca0TJH9p172s8ZnL8A2w== X-Received: by 2002:a05:6870:911f:b0:183:c9a0:ef36 with SMTP id o31-20020a056870911f00b00183c9a0ef36mr64998oae.40.1680804255245; Thu, 06 Apr 2023 11:04:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 05/20] target/riscv: remove cpu->cfg.ext_a Date: Thu, 6 Apr 2023 15:03:36 -0300 Message-Id: <20230406180351.570807-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804478190100003 Content-Type: text/plain; charset="utf-8" Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 16 ++++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b234a03d0..3770fd4f6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -819,13 +819,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && + riscv_has_ext(env, RVA) && + cpu->cfg.ext_f && cpu->cfg.ext_d && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; cpu->cfg.ext_f =3D true; cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; @@ -869,7 +868,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1160,7 +1159,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_m) { ext |=3D RVM; } - if (riscv_cpu_cfg(env)->ext_a) { + if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } if (riscv_cpu_cfg(env)->ext_f) { @@ -1496,7 +1495,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visito= r *v, const char *name, visit_type_bool(v, name, &value, errp); } =20 -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + {.name =3D "a", .description =3D "Atomic instructions", + .misa_bit =3D RVA, .enabled =3D true}, +}; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) { @@ -1522,7 +1524,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_a =3D misa_ext & RVA; cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cbf3de2708..1d1a17d85b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -426,7 +426,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_a; bool ext_f; bool ext_d; bool ext_c; --=20 2.39.2