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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YMcBcOMKiOCRPkvJPsLKtCK2KcBHaIOtwtePnGbSRc8=; b=E1CZpAU1YW74/bnzn5qMCtHYhaujTVT1Lp7E9R28/rSFaLrLfj9O1cqCej0J9dRaAY VMMtrXhakmjHyZq9zKvrmfkvojg+XrhJoiT7m2sVJAuiF5Jkd+M78CdaEOCtI0sbPWJW SZcfqbyk2apEE59yfnUnL90+QFAMIpYvbTBg52acIXrDWa9dtOhevufR7qwx4ykJYAF4 b8/jdF7ErJQX8oxhHYyQl1y31q0DuKM3pl+omwRjKmYF22v0xvpDl0VFKeyGeOvGh502 oyEu9zKR+67BXZlzBDxiKWUJhBFlVwn8cj4CreVTHAXQMgikGmH54OARhitWK4tdiNN6 wiAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804279; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YMcBcOMKiOCRPkvJPsLKtCK2KcBHaIOtwtePnGbSRc8=; b=XX+PSNA64/6uAN2ySezrq1a7KmEoFqSwDFfJ+fEON9efydEVdLDBy0hXLgGcOzPIN7 rxENYyYaW/LyU4Xjn2poHWGOjLVFzL2eKgL55hgMQRp33UHEUUpEGw0lPfC3EbWS1INN EpE+Wq7tWIEOdDc6ZE0CqVZAVzbptwNOcoJ+6iW33GfOaDkzNnenDqKUVV5Vj0zS9360 IHdnzyzlhUhkVH47J2dfwd3hJiwMyBC6HzVIKv4Hazwqsxw5i17N6JJh57/PBIihtTIR 7fBercTjK5efoZzqBxgWGID/cNT+3vTSD4So+XiS5LfIRYBra6bkUhJk6aK1WyZLz9mN w75w== X-Gm-Message-State: AAQBX9c9aH1s3m6MmFQW+SeTZLGct6b4lnCe0VbEqcSfJf0b6Du/iTYC gD5PxklyqklbUORg05as1agwleFvgKFbEAEIaEk= X-Google-Smtp-Source: AKy350ZzYfkdX+WYEw1EjhI0IFuZ+CYVtiv8DjhzRagzHvnQ5aQXidCHVaFxfhVY9UONbVbuaRMF3A== X-Received: by 2002:a05:6870:968f:b0:177:b463:9dcf with SMTP id o15-20020a056870968f00b00177b4639dcfmr51733oaq.46.1680804279669; Thu, 06 Apr 2023 11:04:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 13/20] target/riscv: remove cpu->cfg.ext_u Date: Thu, 6 Apr 2023 15:03:44 -0300 Message-Id: <20230406180351.570807-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804480713100011 Content-Type: text/plain; charset="utf-8" Create a new "u" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are replaced with riscv_has_ext(env, RVU). Remove the old "u" property and 'ext_u' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 9 ++++----- target/riscv/cpu.h | 1 - 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cded82ac7a..9565495839 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -407,7 +407,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_u =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_zfh =3D true; cpu->cfg.mmu =3D true; @@ -842,7 +841,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { error_setg(errp, "Setting S extension without U extension is illegal"); return; @@ -1170,7 +1169,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVS)) { ext |=3D RVS; } - if (riscv_cpu_cfg(env)->ext_u) { + if (riscv_has_ext(env, RVU)) { ext |=3D RVU; } if (riscv_cpu_cfg(env)->ext_h) { @@ -1508,6 +1507,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVM, .enabled =3D true}, {.name =3D "s", .description =3D "Supervisor-level instructions", .misa_bit =3D RVS, .enabled =3D true}, + {.name =3D "u", .description =3D "User-level instructions", + .misa_bit =3D RVU, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1531,7 +1532,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), @@ -1647,7 +1647,6 @@ static void register_cpu_props(Object *obj) */ if (cpu->env.misa_ext !=3D 0) { cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; cpu->cfg.ext_j =3D misa_ext & RVJ; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8b8e541e5f..486061589e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_u; bool ext_h; bool ext_j; bool ext_v; --=20 2.39.2