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([191.255.108.232]) by smtp.gmail.com with ESMTPSA id g4-20020a056870d20400b0018045663fc5sm906309oac.48.2023.04.06.11.04.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 11:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680804273; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kV7z09+98ddMxW+lPuQeVv6kSGaKTK/aK1AU+q2WtVg=; b=Kc2V2GluUYxAHaM2MKAM7W7YcaF9LBCB0VP8U6/Xz23vrxV7CbGe+wprANq8TLWRVr Sav8M6JkuoMKUA0HmegQ+JBB9W57s98KwmP8zdF0Xi9RHgstVMf0XApYwR/dULz///zc Vbb1XznUWqdMNK+vP5/eidZWC85mTW1lQ5PdSssOuyk6y/C2rRcN2v8VSKXtksiqmewK 8xT3Qa3uPb199w9DjZXOtqb6d96WzY7P+apTosKZDT5nYxu+uK0GVYFJYJBV96yeKdUw fl5hJkYDY08fZmCNMRd2XdphyXnhqzrSkcGPLkScMQnA9U6v7Wcwp+eV3fxCYjIqAm7C ba6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680804273; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kV7z09+98ddMxW+lPuQeVv6kSGaKTK/aK1AU+q2WtVg=; b=5qmX9i/gHDSPTXZhfqeLZu1JTar345pz3nB1xkC4w4i+LXmVGmuj+7Fe3Pxlq1tXU7 BXjfC9XheeJSB6kl9DKYNSzzEUJcBy8EeeBIDy7gmg11kKFmQjmMuDQeilrPH2FvO0EF l5zMbAMfU92SAeqmest4EISYKWb9Vr8W+c87CLOk9RilMqMc0cN0AYh9TXNc70v+NPJY 4NTXYCI036NaVaZz+5N9txLqUS7/iAy8fPW+0WDURFaLsoBpccE5VQJANY2UaX6Zmlpu 9Ks7XGwKn94UPzLFltDO47KDpqnXV1Bardm/JHJMGASxRilfy8regKluy5CC2r2z9jhG kAOA== X-Gm-Message-State: AAQBX9eWbH5lgWUKNLctfktqvCH9tIAijcLDJFXVsnoFLmMdPdWCT7gi D/F+EIYqiC3OmuDT/p/FIPzba+aX+x5+ZAkAVYo= X-Google-Smtp-Source: AKy350YV90xy+hlW+GBPL8Fm7T+FEq4HIs8ZCtkBbRtEByD9QtN90D2Biavx8j6Gz7eJAPznvKbWiA== X-Received: by 2002:a05:6870:b489:b0:176:53a1:b65c with SMTP id y9-20020a056870b48900b0017653a1b65cmr148750oap.11.1680804273439; Thu, 06 Apr 2023 11:04:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 11/20] target/riscv: remove cpu->cfg.ext_m Date: Thu, 6 Apr 2023 15:03:42 -0300 Message-Id: <20230406180351.570807-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230406180351.570807-1-dbarboza@ventanamicro.com> References: <20230406180351.570807-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680804449889100001 Content-Type: text/plain; charset="utf-8" Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 33db4fa4b2..24640450c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -817,13 +817,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -1153,7 +1153,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } - if (riscv_cpu_cfg(env)->ext_m) { + if (riscv_has_ext(env, RVM)) { ext |=3D RVM; } if (riscv_has_ext(env, RVA)) { @@ -1505,6 +1505,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVI, .enabled =3D true}, {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", .misa_bit =3D RVE, .enabled =3D false}, + {.name =3D "m", .description =3D "Integer multiplication and division", + .misa_bit =3D RVM, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1528,7 +1530,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1645,7 +1646,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2b42de60b1..71540a33ec 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -423,7 +423,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_m; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2