From nobody Mon Feb 9 20:35:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680685220868109.88698979747289; Wed, 5 Apr 2023 02:00:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pjyyQ-0000hV-6p; Wed, 05 Apr 2023 04:58:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pjyyN-0000fv-EV; Wed, 05 Apr 2023 04:58:31 -0400 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pjyyI-0003Cr-QQ; Wed, 05 Apr 2023 04:58:31 -0400 Received: from localhost.localdomain (unknown [180.175.29.170]) by APP-05 (Coremail) with SMTP id zQCowAAH+BQoOC1kWY5GDg--.24854S3; Wed, 05 Apr 2023 16:58:18 +0800 (CST) From: Weiwei Li To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li , Richard Henderson Subject: [PATCH v3 1/4] target/riscv: Remove riscv_cpu_virt_enabled() Date: Wed, 5 Apr 2023 16:58:10 +0800 Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405085813.40643-1-liweiwei@iscas.ac.cn> References: <20230405085813.40643-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAAH+BQoOC1kWY5GDg--.24854S3 X-Coremail-Antispam: 1UD129KBjvAXoWfAr1UuF17KFykJF4kJr4DXFb_yoW8KF45Ao Z7Kr409an8Gw1S9w1vvr1UtryUXF1ktrsYqrsrKrZ3W3ZruF1rXr45Kr4UAa47tFWftFW8 Xa4xGF12ga4xAa43n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOU7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r18M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAF wI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc4 0Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AK xVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr 1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbec_DUU UUU== X-Originating-IP: [180.175.29.170] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1680685221511100003 Content-Type: text/plain; charset="utf-8" Directly use env->virt_enabled instead. Suggested-by: LIU Zhiwei Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 51 ++++++++++++++++++--------------------- target/riscv/csr.c | 46 +++++++++++++++++------------------ target/riscv/debug.c | 10 ++++---- target/riscv/op_helper.c | 18 +++++++------- target/riscv/pmu.c | 4 +-- target/riscv/translate.c | 2 +- 8 files changed, 64 insertions(+), 70 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd9e7bdce6..c304deabd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,7 +556,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) =20 #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s %d\n", "V =3D ", riscv_cpu_virt_enabled= (env)); + qemu_fprintf(f, " %s %d\n", "V =3D ", env->virt_enabled); } #endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ff6b3c6720..995192757a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -585,7 +585,6 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); -bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b0e094a933..fbcdec3c06 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -93,8 +93,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, =20 if (riscv_has_ext(env, RVH)) { if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + (env->priv =3D=3D PRV_S && !env->virt_enabled) || + (env->priv =3D=3D PRV_U && !env->virt_enabled && get_field(env->hstatus, HSTATUS_HU))) { flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } @@ -391,7 +391,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) uint64_t irqs, pending, mie, hsie, vsie; =20 /* Determine interrupt enable state of all privilege modes */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { mie =3D 1; hsie =3D 1; vsie =3D (env->priv < PRV_S) || @@ -452,7 +452,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) bool riscv_cpu_fp_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_FS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)= ) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { return false; } return true; @@ -465,7 +465,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) bool riscv_cpu_vector_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_VS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)= ) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { return false; } return true; @@ -483,7 +483,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) if (riscv_has_ext(env, RVF)) { mstatus_mask |=3D MSTATUS_FS; } - bool current_virt =3D riscv_cpu_virt_enabled(env); + bool current_virt =3D env->virt_enabled; =20 g_assert(riscv_has_ext(env, RVH)); =20 @@ -558,11 +558,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen) env->geilen =3D geilen; } =20 -bool riscv_cpu_virt_enabled(CPURISCVState *env) -{ - return env->virt_enabled; -} - /* This function can only be called to set virt when RVH is enabled */ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) { @@ -609,7 +604,7 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint6= 4_t mask, CPUState *cs =3D env_cpu(env); uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } @@ -768,7 +763,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (!riscv_cpu_virt_enabled(env) && two_stage) { + if (!env->virt_enabled && two_stage) { use_background =3D true; } =20 @@ -931,7 +926,7 @@ restart: bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; bool hade =3D env->menvcfg & MENVCFG_HADE; =20 - if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { + if (first_stage && two_stage && env->virt_enabled) { pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); hade =3D hade && (env->henvcfg & HENVCFG_HADE); } @@ -1091,7 +1086,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, =20 switch (access_type) { case MMU_INST_FETCH: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if (env->virt_enabled && !first_stage) { cs->exception_index =3D RISCV_EXCP_INST_GUEST_PAGE_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -1131,11 +1126,11 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, - true, riscv_cpu_virt_enabled(env), true)) { + true, env->virt_enabled, true)) { return -1; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 0, mmu_idx, false, true, true)) { return -1; @@ -1163,7 +1158,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, } =20 env->badaddr =3D addr; - env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + env->two_stage_lookup =3D env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); @@ -1189,7 +1184,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; - env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + env->two_stage_lookup =3D env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); @@ -1253,7 +1248,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } =20 pmu_tlb_fill_incr_ctr(cpu, access_type); - if (riscv_cpu_virt_enabled(env) || + if (env->virt_enabled || ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ @@ -1351,7 +1346,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } else { raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, - riscv_cpu_virt_enabled(env) || + env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx), two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); @@ -1658,9 +1653,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 if (env->priv =3D=3D PRV_M) { cause =3D RISCV_EXCP_M_ECALL; - } else if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(en= v)) { + } else if (env->priv =3D=3D PRV_S && env->virt_enabled) { cause =3D RISCV_EXCP_VS_ECALL; - } else if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(e= nv)) { + } else if (env->priv =3D=3D PRV_S && !env->virt_enabled) { cause =3D RISCV_EXCP_S_ECALL; } else if (env->priv =3D=3D PRV_U) { cause =3D RISCV_EXCP_U_ECALL; @@ -1683,7 +1678,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; =20 - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { + if (env->virt_enabled && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -1694,7 +1689,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause =3D cause - 1; } write_gva =3D false; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, @@ -1728,12 +1723,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else { /* handle the trap in M-mode */ if (riscv_has_ext(env, RVH)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { riscv_cpu_swap_hypervisor_regs(env); } env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { + env->virt_enabled); + if (env->virt_enabled && tval) { env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 777d7fbac0..41e56012d5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -45,7 +45,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) #if !defined(CONFIG_USER_ONLY) RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; =20 if (env->priv =3D=3D PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_NONE; @@ -135,7 +135,7 @@ skip_ext_pmu_check: return RISCV_EXCP_ILLEGAL_INST; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!get_field(env->hcounteren, ctr_mask) || (env->priv =3D=3D PRV_U && !get_field(env->scounteren, ctr_mas= k))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -365,7 +365,7 @@ static RISCVException hstateenh(CPURISCVState *env, int= csrno) =20 static RISCVException sstateen(CPURISCVState *env, int csrno) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; =20 if (!riscv_cpu_cfg(env)->ext_smstateen) { @@ -430,7 +430,7 @@ static RISCVException sstc(CPURISCVState *env, int csrn= o) return RISCV_EXCP_ILLEGAL_INST; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -536,7 +536,7 @@ static RISCVException seed(CPURISCVState *env, int csrn= o) */ if (env->priv =3D=3D PRV_M) { return RISCV_EXCP_NONE; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { if (env->mseccfg & MSECCFG_SSEED) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } else { @@ -964,7 +964,7 @@ static int read_scountovf(CPURISCVState *env, int csrno= , target_ulong *val) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -977,7 +977,7 @@ static RISCVException read_time(CPURISCVState *env, int= csrno, static RISCVException read_timeh(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -1031,7 +1031,7 @@ static RISCVException write_vstimecmph(CPURISCVState = *env, int csrno, static RISCVException read_stimecmp(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val =3D env->vstimecmp; } else { *val =3D env->stimecmp; @@ -1043,7 +1043,7 @@ static RISCVException read_stimecmp(CPURISCVState *en= v, int csrno, static RISCVException read_stimecmph(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val =3D env->vstimecmp >> 32; } else { *val =3D env->stimecmp >> 32; @@ -1055,7 +1055,7 @@ static RISCVException read_stimecmph(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmp(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1076,7 +1076,7 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmph(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1530,7 +1530,7 @@ static int read_mtopi(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) { - if (!riscv_cpu_virt_enabled(env)) { + if (!env->virt_enabled) { return csrno; } =20 @@ -1687,7 +1687,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t= arget_ulong *val, =20 done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -1741,7 +1741,7 @@ static int rmw_xtopei(CPURISCVState *env, int csrno, = target_ulong *val, =20 done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -2171,7 +2171,7 @@ static RISCVException write_hstateenh_1_3(CPURISCVSta= te *env, int csrno, static RISCVException read_sstateen(CPURISCVState *env, int csrno, target_ulong *val) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; =20 *val =3D env->sstateen[index] & env->mstateen[index]; @@ -2185,7 +2185,7 @@ static RISCVException read_sstateen(CPURISCVState *en= v, int csrno, static RISCVException write_sstateen(CPURISCVState *env, int csrno, uint64_t mask, target_ulong new_val) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; uint64_t wr_mask; uint64_t *reg; @@ -2380,7 +2380,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, i= nt csrno, RISCVException ret; uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2590,7 +2590,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, RISCVException ret; uint64_t mask =3D env->mideleg & sip_writable_mask; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2783,7 +2783,7 @@ static int read_stopi(CPURISCVState *env, int csrno, = target_ulong *val) int irq; uint8_t iprio; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return read_vstopi(env, CSR_VSTOPI, val); } =20 @@ -3128,7 +3128,7 @@ static int read_hvipriox(CPURISCVState *env, int firs= t_index, =20 /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3154,7 +3154,7 @@ static int write_hvipriox(CPURISCVState *env, int fir= st_index, =20 /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3809,7 +3809,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, int csr_priv, effective_priv =3D env->priv; =20 if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S && - !riscv_cpu_virt_enabled(env)) { + !env->virt_enabled) { /* * We are in HS mode. Add 1 to the effective privledge level to * allow us to access the Hypervisor CSRs. @@ -3819,7 +3819,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, =20 csr_priv =3D get_field(csrno, 0x300); if (!env->debugger && (effective_priv < csr_priv)) { - if (csr_priv =3D=3D (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { + if (csr_priv =3D=3D (PRV_S + 1) && env->virt_enabled) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index b091293069..1f7aed23c9 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -515,7 +515,7 @@ itrigger_set_count(CPURISCVState *env, int index, int v= alue) static bool check_itrigger_priv(CPURISCVState *env, int index) { target_ulong tdata1 =3D env->tdata1[index]; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ return (get_field(tdata1, ITRIGGER_VS) =3D=3D env->priv) || (get_field(tdata1, ITRIGGER_VU) =3D=3D env->priv); @@ -787,7 +787,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } =20 @@ -806,7 +806,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) pc =3D env->tdata2[i]; =20 if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level= */ if ((ctrl >> 23) & BIT(env->priv)) { return true; @@ -845,7 +845,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } =20 @@ -880,7 +880,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) } =20 if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ if ((ctrl >> 23) & BIT(env->priv)) { return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eecae9547..c0c4ced7f0 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -140,7 +140,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, targ= et_ulong envbits, riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - if (riscv_cpu_virt_enabled(env) && + if (env->virt_enabled && (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) || ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); @@ -278,7 +278,7 @@ target_ulong helper_sret(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTS= R)) { + if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 @@ -293,7 +293,7 @@ target_ulong helper_sret(CPURISCVState *env) } env->mstatus =3D mstatus; =20 - if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + if (riscv_has_ext(env, RVH) && !env->virt_enabled) { /* We support Hypervisor extensions and virtulisation is disabled = */ target_ulong hstatus =3D env->hstatus; =20 @@ -365,9 +365,9 @@ void helper_wfi(CPURISCVState *env) bool prv_s =3D env->priv =3D=3D PRV_S; =20 if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)= ) || - (rvs && prv_u && !riscv_cpu_virt_enabled(env))) { + (rvs && prv_u && !env->virt_enabled)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_cpu_virt_enabled(env) && (prv_u || + } else if (env->virt_enabled && (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { @@ -384,7 +384,7 @@ void helper_tlb_flush(CPURISCVState *env) (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + } else if (riscv_has_ext(env, RVH) && env->virt_enabled && get_field(env->hstatus, HSTATUS_VTVM)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { @@ -402,12 +402,12 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); =20 - if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(env)) { + if (env->priv =3D=3D PRV_S && env->virt_enabled) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env))) { + (env->priv =3D=3D PRV_S && !env->virt_enabled)) { tlb_flush(cs); return; } @@ -417,7 +417,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env) =20 void helper_hyp_gvma_tlb_flush(CPURISCVState *env) { - if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && + if (env->priv =3D=3D PRV_S && !env->virt_enabled && get_field(env->mstatus, MSTATUS_TVM)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 96ce2dbe49..48ad60be2b 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -109,7 +109,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint3= 2_t ctr_idx) CPURISCVState *env =3D &cpu->env; target_ulong max_val =3D UINT32_MAX; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - bool virt_on =3D riscv_cpu_virt_enabled(env); + bool virt_on =3D env->virt_enabled; =20 /* Privilege mode filtering */ if ((env->priv =3D=3D PRV_M && @@ -150,7 +150,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint3= 2_t ctr_idx) CPURISCVState *env =3D &cpu->env; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t max_val =3D UINT64_MAX; - bool virt_on =3D riscv_cpu_virt_enabled(env); + bool virt_on =3D env->virt_enabled; =20 /* Privilege mode filtering */ if ((env->priv =3D=3D PRV_M && diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5dddac44bc..03748f72e6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1169,7 +1169,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->priv_ver =3D env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); + ctx->virt_enabled =3D env->virt_enabled; } else { ctx->virt_enabled =3D false; } --=20 2.25.1