From nobody Sat May 18 20:15:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680685220868109.88698979747289; Wed, 5 Apr 2023 02:00:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pjyyQ-0000hV-6p; Wed, 05 Apr 2023 04:58:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pjyyN-0000fv-EV; Wed, 05 Apr 2023 04:58:31 -0400 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pjyyI-0003Cr-QQ; Wed, 05 Apr 2023 04:58:31 -0400 Received: from localhost.localdomain (unknown [180.175.29.170]) by APP-05 (Coremail) with SMTP id zQCowAAH+BQoOC1kWY5GDg--.24854S3; Wed, 05 Apr 2023 16:58:18 +0800 (CST) From: Weiwei Li To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li , Richard Henderson Subject: [PATCH v3 1/4] target/riscv: Remove riscv_cpu_virt_enabled() Date: Wed, 5 Apr 2023 16:58:10 +0800 Message-Id: <20230405085813.40643-2-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405085813.40643-1-liweiwei@iscas.ac.cn> References: <20230405085813.40643-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAAH+BQoOC1kWY5GDg--.24854S3 X-Coremail-Antispam: 1UD129KBjvAXoWfAr1UuF17KFykJF4kJr4DXFb_yoW8KF45Ao Z7Kr409an8Gw1S9w1vvr1UtryUXF1ktrsYqrsrKrZ3W3ZruF1rXr45Kr4UAa47tFWftFW8 Xa4xGF12ga4xAa43n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOU7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r18M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAF wI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc4 0Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AK xVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr 1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbec_DUU UUU== X-Originating-IP: [180.175.29.170] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1680685221511100003 Content-Type: text/plain; charset="utf-8" Directly use env->virt_enabled instead. Suggested-by: LIU Zhiwei Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 51 ++++++++++++++++++--------------------- target/riscv/csr.c | 46 +++++++++++++++++------------------ target/riscv/debug.c | 10 ++++---- target/riscv/op_helper.c | 18 +++++++------- target/riscv/pmu.c | 4 +-- target/riscv/translate.c | 2 +- 8 files changed, 64 insertions(+), 70 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd9e7bdce6..c304deabd7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,7 +556,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) =20 #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - qemu_fprintf(f, " %s %d\n", "V =3D ", riscv_cpu_virt_enabled= (env)); + qemu_fprintf(f, " %s %d\n", "V =3D ", env->virt_enabled); } #endif qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ff6b3c6720..995192757a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -585,7 +585,6 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env); target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); -bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b0e094a933..fbcdec3c06 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -93,8 +93,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, =20 if (riscv_has_ext(env, RVH)) { if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + (env->priv =3D=3D PRV_S && !env->virt_enabled) || + (env->priv =3D=3D PRV_U && !env->virt_enabled && get_field(env->hstatus, HSTATUS_HU))) { flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } @@ -391,7 +391,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *e= nv) uint64_t irqs, pending, mie, hsie, vsie; =20 /* Determine interrupt enable state of all privilege modes */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { mie =3D 1; hsie =3D 1; vsie =3D (env->priv < PRV_S) || @@ -452,7 +452,7 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) bool riscv_cpu_fp_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_FS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)= ) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { return false; } return true; @@ -465,7 +465,7 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) bool riscv_cpu_vector_enabled(CPURISCVState *env) { if (env->mstatus & MSTATUS_VS) { - if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)= ) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { return false; } return true; @@ -483,7 +483,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) if (riscv_has_ext(env, RVF)) { mstatus_mask |=3D MSTATUS_FS; } - bool current_virt =3D riscv_cpu_virt_enabled(env); + bool current_virt =3D env->virt_enabled; =20 g_assert(riscv_has_ext(env, RVH)); =20 @@ -558,11 +558,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen) env->geilen =3D geilen; } =20 -bool riscv_cpu_virt_enabled(CPURISCVState *env) -{ - return env->virt_enabled; -} - /* This function can only be called to set virt when RVH is enabled */ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) { @@ -609,7 +604,7 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint6= 4_t mask, CPUState *cs =3D env_cpu(env); uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } @@ -768,7 +763,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (!riscv_cpu_virt_enabled(env) && two_stage) { + if (!env->virt_enabled && two_stage) { use_background =3D true; } =20 @@ -931,7 +926,7 @@ restart: bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; bool hade =3D env->menvcfg & MENVCFG_HADE; =20 - if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { + if (first_stage && two_stage && env->virt_enabled) { pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); hade =3D hade && (env->henvcfg & HENVCFG_HADE); } @@ -1091,7 +1086,7 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, =20 switch (access_type) { case MMU_INST_FETCH: - if (riscv_cpu_virt_enabled(env) && !first_stage) { + if (env->virt_enabled && !first_stage) { cs->exception_index =3D RISCV_EXCP_INST_GUEST_PAGE_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -1131,11 +1126,11 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, - true, riscv_cpu_virt_enabled(env), true)) { + true, env->virt_enabled, true)) { return -1; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, 0, mmu_idx, false, true, true)) { return -1; @@ -1163,7 +1158,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, } =20 env->badaddr =3D addr; - env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + env->two_stage_lookup =3D env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); @@ -1189,7 +1184,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, g_assert_not_reached(); } env->badaddr =3D addr; - env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + env->two_stage_lookup =3D env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx); env->two_stage_indirect_lookup =3D false; cpu_loop_exit_restore(cs, retaddr); @@ -1253,7 +1248,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } =20 pmu_tlb_fill_incr_ctr(cpu, access_type); - if (riscv_cpu_virt_enabled(env) || + if (env->virt_enabled || ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ @@ -1351,7 +1346,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } else { raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, - riscv_cpu_virt_enabled(env) || + env->virt_enabled || riscv_cpu_two_stage_lookup(mmu_idx), two_stage_indirect_error); cpu_loop_exit_restore(cs, retaddr); @@ -1658,9 +1653,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 if (env->priv =3D=3D PRV_M) { cause =3D RISCV_EXCP_M_ECALL; - } else if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(en= v)) { + } else if (env->priv =3D=3D PRV_S && env->virt_enabled) { cause =3D RISCV_EXCP_VS_ECALL; - } else if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(e= nv)) { + } else if (env->priv =3D=3D PRV_S && !env->virt_enabled) { cause =3D RISCV_EXCP_S_ECALL; } else if (env->priv =3D=3D PRV_U) { cause =3D RISCV_EXCP_U_ECALL; @@ -1683,7 +1678,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; =20 - if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) { + if (env->virt_enabled && ((hdeleg >> cause) & 1)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -1694,7 +1689,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) cause =3D cause - 1; } write_gva =3D false; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, @@ -1728,12 +1723,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) } else { /* handle the trap in M-mode */ if (riscv_has_ext(env, RVH)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { riscv_cpu_swap_hypervisor_regs(env); } env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { + env->virt_enabled); + if (env->virt_enabled && tval) { env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 777d7fbac0..41e56012d5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -45,7 +45,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) #if !defined(CONFIG_USER_ONLY) RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; =20 if (env->priv =3D=3D PRV_M || !riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_NONE; @@ -135,7 +135,7 @@ skip_ext_pmu_check: return RISCV_EXCP_ILLEGAL_INST; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!get_field(env->hcounteren, ctr_mask) || (env->priv =3D=3D PRV_U && !get_field(env->scounteren, ctr_mas= k))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -365,7 +365,7 @@ static RISCVException hstateenh(CPURISCVState *env, int= csrno) =20 static RISCVException sstateen(CPURISCVState *env, int csrno) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; =20 if (!riscv_cpu_cfg(env)->ext_smstateen) { @@ -430,7 +430,7 @@ static RISCVException sstc(CPURISCVState *env, int csrn= o) return RISCV_EXCP_ILLEGAL_INST; } =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (!(get_field(env->hcounteren, COUNTEREN_TM) && get_field(env->henvcfg, HENVCFG_STCE))) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -536,7 +536,7 @@ static RISCVException seed(CPURISCVState *env, int csrn= o) */ if (env->priv =3D=3D PRV_M) { return RISCV_EXCP_NONE; - } else if (riscv_cpu_virt_enabled(env)) { + } else if (env->virt_enabled) { if (env->mseccfg & MSECCFG_SSEED) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } else { @@ -964,7 +964,7 @@ static int read_scountovf(CPURISCVState *env, int csrno= , target_ulong *val) static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -977,7 +977,7 @@ static RISCVException read_time(CPURISCVState *env, int= csrno, static RISCVException read_timeh(CPURISCVState *env, int csrno, target_ulong *val) { - uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; + uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; @@ -1031,7 +1031,7 @@ static RISCVException write_vstimecmph(CPURISCVState = *env, int csrno, static RISCVException read_stimecmp(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val =3D env->vstimecmp; } else { *val =3D env->stimecmp; @@ -1043,7 +1043,7 @@ static RISCVException read_stimecmp(CPURISCVState *en= v, int csrno, static RISCVException read_stimecmph(CPURISCVState *env, int csrno, target_ulong *val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { *val =3D env->vstimecmp >> 32; } else { *val =3D env->stimecmp >> 32; @@ -1055,7 +1055,7 @@ static RISCVException read_stimecmph(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmp(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1076,7 +1076,7 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmph(CPURISCVState *env, int csrno, target_ulong val) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -1530,7 +1530,7 @@ static int read_mtopi(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno) { - if (!riscv_cpu_virt_enabled(env)) { + if (!env->virt_enabled) { return csrno; } =20 @@ -1687,7 +1687,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t= arget_ulong *val, =20 done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -1741,7 +1741,7 @@ static int rmw_xtopei(CPURISCVState *env, int csrno, = target_ulong *val, =20 done: if (ret) { - return (riscv_cpu_virt_enabled(env) && virt) ? + return (env->virt_enabled && virt) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } return RISCV_EXCP_NONE; @@ -2171,7 +2171,7 @@ static RISCVException write_hstateenh_1_3(CPURISCVSta= te *env, int csrno, static RISCVException read_sstateen(CPURISCVState *env, int csrno, target_ulong *val) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; =20 *val =3D env->sstateen[index] & env->mstateen[index]; @@ -2185,7 +2185,7 @@ static RISCVException read_sstateen(CPURISCVState *en= v, int csrno, static RISCVException write_sstateen(CPURISCVState *env, int csrno, uint64_t mask, target_ulong new_val) { - bool virt =3D riscv_cpu_virt_enabled(env); + bool virt =3D env->virt_enabled; int index =3D csrno - CSR_SSTATEEN0; uint64_t wr_mask; uint64_t *reg; @@ -2380,7 +2380,7 @@ static RISCVException rmw_sie64(CPURISCVState *env, i= nt csrno, RISCVException ret; uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2590,7 +2590,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, RISCVException ret; uint64_t mask =3D env->mideleg & sip_writable_mask; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } @@ -2783,7 +2783,7 @@ static int read_stopi(CPURISCVState *env, int csrno, = target_ulong *val) int irq; uint8_t iprio; =20 - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return read_vstopi(env, CSR_VSTOPI, val); } =20 @@ -3128,7 +3128,7 @@ static int read_hvipriox(CPURISCVState *env, int firs= t_index, =20 /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3154,7 +3154,7 @@ static int write_hvipriox(CPURISCVState *env, int fir= st_index, =20 /* First index has to be a multiple of number of irqs per register */ if (first_index % num_irqs) { - return (riscv_cpu_virt_enabled(env)) ? + return (env->virt_enabled) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3809,7 +3809,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, int csr_priv, effective_priv =3D env->priv; =20 if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_S && - !riscv_cpu_virt_enabled(env)) { + !env->virt_enabled) { /* * We are in HS mode. Add 1 to the effective privledge level to * allow us to access the Hypervisor CSRs. @@ -3819,7 +3819,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, =20 csr_priv =3D get_field(csrno, 0x300); if (!env->debugger && (effective_priv < csr_priv)) { - if (csr_priv =3D=3D (PRV_S + 1) && riscv_cpu_virt_enabled(env)) { + if (csr_priv =3D=3D (PRV_S + 1) && env->virt_enabled) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index b091293069..1f7aed23c9 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -515,7 +515,7 @@ itrigger_set_count(CPURISCVState *env, int index, int v= alue) static bool check_itrigger_priv(CPURISCVState *env, int index) { target_ulong tdata1 =3D env->tdata1[index]; - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ return (get_field(tdata1, ITRIGGER_VS) =3D=3D env->priv) || (get_field(tdata1, ITRIGGER_VU) =3D=3D env->priv); @@ -787,7 +787,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } =20 @@ -806,7 +806,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) pc =3D env->tdata2[i]; =20 if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level= */ if ((ctrl >> 23) & BIT(env->priv)) { return true; @@ -845,7 +845,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: /* type 2 trigger cannot be fired in VU/VS mode */ - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { return false; } =20 @@ -880,7 +880,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPU= Watchpoint *wp) } =20 if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - if (riscv_cpu_virt_enabled(env)) { + if (env->virt_enabled) { /* check VU/VS bit against current privilege level */ if ((ctrl >> 23) & BIT(env->priv)) { return true; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eecae9547..c0c4ced7f0 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -140,7 +140,7 @@ static void check_zicbo_envcfg(CPURISCVState *env, targ= et_ulong envbits, riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } =20 - if (riscv_cpu_virt_enabled(env) && + if (env->virt_enabled && (((env->priv < PRV_H) && !get_field(env->henvcfg, envbits)) || ((env->priv < PRV_S) && !get_field(env->senvcfg, envbits)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, ra); @@ -278,7 +278,7 @@ target_ulong helper_sret(CPURISCVState *env) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 - if (riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTS= R)) { + if (env->virt_enabled && get_field(env->hstatus, HSTATUS_VTSR)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 @@ -293,7 +293,7 @@ target_ulong helper_sret(CPURISCVState *env) } env->mstatus =3D mstatus; =20 - if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) { + if (riscv_has_ext(env, RVH) && !env->virt_enabled) { /* We support Hypervisor extensions and virtulisation is disabled = */ target_ulong hstatus =3D env->hstatus; =20 @@ -365,9 +365,9 @@ void helper_wfi(CPURISCVState *env) bool prv_s =3D env->priv =3D=3D PRV_S; =20 if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)= ) || - (rvs && prv_u && !riscv_cpu_virt_enabled(env))) { + (rvs && prv_u && !env->virt_enabled)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_cpu_virt_enabled(env) && (prv_u || + } else if (env->virt_enabled && (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { @@ -384,7 +384,7 @@ void helper_tlb_flush(CPURISCVState *env) (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && + } else if (riscv_has_ext(env, RVH) && env->virt_enabled && get_field(env->hstatus, HSTATUS_VTVM)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { @@ -402,12 +402,12 @@ void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs =3D env_cpu(env); =20 - if (env->priv =3D=3D PRV_S && riscv_cpu_virt_enabled(env)) { + if (env->priv =3D=3D PRV_S && env->virt_enabled) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } =20 if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env))) { + (env->priv =3D=3D PRV_S && !env->virt_enabled)) { tlb_flush(cs); return; } @@ -417,7 +417,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env) =20 void helper_hyp_gvma_tlb_flush(CPURISCVState *env) { - if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && + if (env->priv =3D=3D PRV_S && !env->virt_enabled && get_field(env->mstatus, MSTATUS_TVM)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 96ce2dbe49..48ad60be2b 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -109,7 +109,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint3= 2_t ctr_idx) CPURISCVState *env =3D &cpu->env; target_ulong max_val =3D UINT32_MAX; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; - bool virt_on =3D riscv_cpu_virt_enabled(env); + bool virt_on =3D env->virt_enabled; =20 /* Privilege mode filtering */ if ((env->priv =3D=3D PRV_M && @@ -150,7 +150,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint3= 2_t ctr_idx) CPURISCVState *env =3D &cpu->env; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t max_val =3D UINT64_MAX; - bool virt_on =3D riscv_cpu_virt_enabled(env); + bool virt_on =3D env->virt_enabled; =20 /* Privilege mode filtering */ if ((env->priv =3D=3D PRV_M && diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5dddac44bc..03748f72e6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1169,7 +1169,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->priv_ver =3D env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { - ctx->virt_enabled =3D riscv_cpu_virt_enabled(env); + ctx->virt_enabled =3D env->virt_enabled; } else { ctx->virt_enabled =3D false; } --=20 2.25.1 From nobody Sat May 18 20:15:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1680685196483630.5936143971576; Wed, 5 Apr 2023 01:59:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pjyyR-0000ir-BJ; Wed, 05 Apr 2023 04:58:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pjyyP-0000hJ-W5; Wed, 05 Apr 2023 04:58:34 -0400 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pjyyI-0003D1-Ru; Wed, 05 Apr 2023 04:58:33 -0400 Received: from localhost.localdomain (unknown [180.175.29.170]) by APP-05 (Coremail) with SMTP id zQCowAAH+BQoOC1kWY5GDg--.24854S4; Wed, 05 Apr 2023 16:58:19 +0800 (CST) From: Weiwei Li To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v3 2/4] target/riscv: Fix format for indentation Date: Wed, 5 Apr 2023 16:58:11 +0800 Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405085813.40643-1-liweiwei@iscas.ac.cn> References: <20230405085813.40643-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAAH+BQoOC1kWY5GDg--.24854S4 X-Coremail-Antispam: 1UD129KBjvAXoWDXFWDWw4rKFyDKr45GrWUCFg_yoWrCFy8Go WfJF4Yyr1fKw1fC3s3ursaqr12gr4Dtws5JFs8KrWSgas7XrWfKFW7tws2vF47tr4fGFWU Zan3t3WrAFn7Aryfn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOU7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAF wI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc4 0Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AK xVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr 1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbdOz7UU UUU== X-Originating-IP: [180.175.29.170] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1680685197330100003 Content-Type: text/plain; charset="utf-8" Fix identation problems, and try to use the same indentation strategy in the same file. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/arch_dump.c | 4 +- target/riscv/cpu.c | 40 +++--- target/riscv/cpu_helper.c | 163 ++++++++++++------------ target/riscv/fpu_helper.c | 24 ++-- target/riscv/insn_trans/trans_rvv.c.inc | 28 ++-- target/riscv/m128_helper.c | 16 +-- target/riscv/machine.c | 18 +-- target/riscv/op_helper.c | 4 +- target/riscv/pmp.c | 19 +-- target/riscv/pmp.h | 9 +- target/riscv/translate.c | 4 +- target/riscv/vector_helper.c | 159 +++++++++++------------ 12 files changed, 247 insertions(+), 241 deletions(-) diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 736a232956..573587810e 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -180,8 +180,8 @@ int cpu_get_dump_info(ArchDumpInfo *info, info->d_class =3D ELFCLASS32; #endif =20 - info->d_endian =3D (env->mstatus & MSTATUS_UBE) !=3D 0 - ? ELFDATA2MSB : ELFDATA2LSB; + info->d_endian =3D (env->mstatus & MSTATUS_UBE) !=3D 0 ? + ELFDATA2MSB : ELFDATA2LSB; =20 return 0; } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c304deabd7..8ed8601399 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -54,7 +54,7 @@ struct isa_ext_data { }; =20 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ -{#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} =20 /** * Here are the ordering rules of extension naming defined by RISC-V @@ -157,29 +157,29 @@ static void isa_ext_update_enabled(RISCVCPU *cpu, } =20 const char * const riscv_int_regnames[] =3D { - "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", - "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", - "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", - "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", - "x28/t3", "x29/t4", "x30/t5", "x31/t6" + "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", + "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", + "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", + "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11= ", + "x28/t3", "x29/t4", "x30/t5", "x31/t6" }; =20 const char * const riscv_int_regnamesh[] =3D { - "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", - "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h= ", - "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h= ", - "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h= ", - "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h= ", - "x30h/t5h", "x31h/t6h" + "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0= h", + "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a= 1h", + "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a= 7h", + "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s= 7h", + "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t= 4h", + "x30h/t5h", "x31h/t6h" }; =20 const char * const riscv_fpr_regnames[] =3D { - "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", - "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", - "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", - "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", - "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", - "f30/ft10", "f31/ft11" + "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", + "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", + "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", + "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", + "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", + "f30/ft10", "f31/ft11" }; =20 static const char * const riscv_excp_names[] =3D { @@ -351,8 +351,8 @@ static void riscv_any_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), - riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); + riscv_cpu_mxl(&RISCV_CPU(obj)->env) =3D=3D MXL_RV32 ? + VM_1_10_SV32 : VM_1_10_SV57); #endif =20 set_priv_version(env, PRIV_VERSION_1_12_0); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fbcdec3c06..8d2547a164 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,12 +68,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ul= ong *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); + FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); + FIELD_EX64(env->vtype, VTYPE, VTA)); flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); + FIELD_EX64(env->vtype, VTYPE, VMA)); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } @@ -95,7 +95,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulon= g *pc, if (env->priv =3D=3D PRV_M || (env->priv =3D=3D PRV_S && !env->virt_enabled) || (env->priv =3D=3D PRV_U && !env->virt_enabled && - get_field(env->hstatus, HSTATUS_HU))) { + get_field(env->hstatus, HSTATUS_HU))) { flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); } =20 @@ -230,75 +230,75 @@ int riscv_cpu_hviprio_index2irq(int index, int *out_i= rq, int *out_rdzero) * ---------------------------------------------------------------- */ static const uint8_t default_iprio[64] =3D { - /* Custom interrupts 48 to 63 */ - [63] =3D IPRIO_MMAXIPRIO, - [62] =3D IPRIO_MMAXIPRIO, - [61] =3D IPRIO_MMAXIPRIO, - [60] =3D IPRIO_MMAXIPRIO, - [59] =3D IPRIO_MMAXIPRIO, - [58] =3D IPRIO_MMAXIPRIO, - [57] =3D IPRIO_MMAXIPRIO, - [56] =3D IPRIO_MMAXIPRIO, - [55] =3D IPRIO_MMAXIPRIO, - [54] =3D IPRIO_MMAXIPRIO, - [53] =3D IPRIO_MMAXIPRIO, - [52] =3D IPRIO_MMAXIPRIO, - [51] =3D IPRIO_MMAXIPRIO, - [50] =3D IPRIO_MMAXIPRIO, - [49] =3D IPRIO_MMAXIPRIO, - [48] =3D IPRIO_MMAXIPRIO, - - /* Custom interrupts 24 to 31 */ - [31] =3D IPRIO_MMAXIPRIO, - [30] =3D IPRIO_MMAXIPRIO, - [29] =3D IPRIO_MMAXIPRIO, - [28] =3D IPRIO_MMAXIPRIO, - [27] =3D IPRIO_MMAXIPRIO, - [26] =3D IPRIO_MMAXIPRIO, - [25] =3D IPRIO_MMAXIPRIO, - [24] =3D IPRIO_MMAXIPRIO, - - [47] =3D IPRIO_DEFAULT_UPPER, - [23] =3D IPRIO_DEFAULT_UPPER + 1, - [46] =3D IPRIO_DEFAULT_UPPER + 2, - [45] =3D IPRIO_DEFAULT_UPPER + 3, - [22] =3D IPRIO_DEFAULT_UPPER + 4, - [44] =3D IPRIO_DEFAULT_UPPER + 5, - - [43] =3D IPRIO_DEFAULT_UPPER + 6, - [21] =3D IPRIO_DEFAULT_UPPER + 7, - [42] =3D IPRIO_DEFAULT_UPPER + 8, - [41] =3D IPRIO_DEFAULT_UPPER + 9, - [20] =3D IPRIO_DEFAULT_UPPER + 10, - [40] =3D IPRIO_DEFAULT_UPPER + 11, - - [11] =3D IPRIO_DEFAULT_M, - [3] =3D IPRIO_DEFAULT_M + 1, - [7] =3D IPRIO_DEFAULT_M + 2, - - [9] =3D IPRIO_DEFAULT_S, - [1] =3D IPRIO_DEFAULT_S + 1, - [5] =3D IPRIO_DEFAULT_S + 2, - - [12] =3D IPRIO_DEFAULT_SGEXT, - - [10] =3D IPRIO_DEFAULT_VS, - [2] =3D IPRIO_DEFAULT_VS + 1, - [6] =3D IPRIO_DEFAULT_VS + 2, - - [39] =3D IPRIO_DEFAULT_LOWER, - [19] =3D IPRIO_DEFAULT_LOWER + 1, - [38] =3D IPRIO_DEFAULT_LOWER + 2, - [37] =3D IPRIO_DEFAULT_LOWER + 3, - [18] =3D IPRIO_DEFAULT_LOWER + 4, - [36] =3D IPRIO_DEFAULT_LOWER + 5, - - [35] =3D IPRIO_DEFAULT_LOWER + 6, - [17] =3D IPRIO_DEFAULT_LOWER + 7, - [34] =3D IPRIO_DEFAULT_LOWER + 8, - [33] =3D IPRIO_DEFAULT_LOWER + 9, - [16] =3D IPRIO_DEFAULT_LOWER + 10, - [32] =3D IPRIO_DEFAULT_LOWER + 11, + /* Custom interrupts 48 to 63 */ + [63] =3D IPRIO_MMAXIPRIO, + [62] =3D IPRIO_MMAXIPRIO, + [61] =3D IPRIO_MMAXIPRIO, + [60] =3D IPRIO_MMAXIPRIO, + [59] =3D IPRIO_MMAXIPRIO, + [58] =3D IPRIO_MMAXIPRIO, + [57] =3D IPRIO_MMAXIPRIO, + [56] =3D IPRIO_MMAXIPRIO, + [55] =3D IPRIO_MMAXIPRIO, + [54] =3D IPRIO_MMAXIPRIO, + [53] =3D IPRIO_MMAXIPRIO, + [52] =3D IPRIO_MMAXIPRIO, + [51] =3D IPRIO_MMAXIPRIO, + [50] =3D IPRIO_MMAXIPRIO, + [49] =3D IPRIO_MMAXIPRIO, + [48] =3D IPRIO_MMAXIPRIO, + + /* Custom interrupts 24 to 31 */ + [31] =3D IPRIO_MMAXIPRIO, + [30] =3D IPRIO_MMAXIPRIO, + [29] =3D IPRIO_MMAXIPRIO, + [28] =3D IPRIO_MMAXIPRIO, + [27] =3D IPRIO_MMAXIPRIO, + [26] =3D IPRIO_MMAXIPRIO, + [25] =3D IPRIO_MMAXIPRIO, + [24] =3D IPRIO_MMAXIPRIO, + + [47] =3D IPRIO_DEFAULT_UPPER, + [23] =3D IPRIO_DEFAULT_UPPER + 1, + [46] =3D IPRIO_DEFAULT_UPPER + 2, + [45] =3D IPRIO_DEFAULT_UPPER + 3, + [22] =3D IPRIO_DEFAULT_UPPER + 4, + [44] =3D IPRIO_DEFAULT_UPPER + 5, + + [43] =3D IPRIO_DEFAULT_UPPER + 6, + [21] =3D IPRIO_DEFAULT_UPPER + 7, + [42] =3D IPRIO_DEFAULT_UPPER + 8, + [41] =3D IPRIO_DEFAULT_UPPER + 9, + [20] =3D IPRIO_DEFAULT_UPPER + 10, + [40] =3D IPRIO_DEFAULT_UPPER + 11, + + [11] =3D IPRIO_DEFAULT_M, + [3] =3D IPRIO_DEFAULT_M + 1, + [7] =3D IPRIO_DEFAULT_M + 2, + + [9] =3D IPRIO_DEFAULT_S, + [1] =3D IPRIO_DEFAULT_S + 1, + [5] =3D IPRIO_DEFAULT_S + 2, + + [12] =3D IPRIO_DEFAULT_SGEXT, + + [10] =3D IPRIO_DEFAULT_VS, + [2] =3D IPRIO_DEFAULT_VS + 1, + [6] =3D IPRIO_DEFAULT_VS + 2, + + [39] =3D IPRIO_DEFAULT_LOWER, + [19] =3D IPRIO_DEFAULT_LOWER + 1, + [38] =3D IPRIO_DEFAULT_LOWER + 2, + [37] =3D IPRIO_DEFAULT_LOWER + 3, + [18] =3D IPRIO_DEFAULT_LOWER + 4, + [36] =3D IPRIO_DEFAULT_LOWER + 5, + + [35] =3D IPRIO_DEFAULT_LOWER + 6, + [17] =3D IPRIO_DEFAULT_LOWER + 7, + [34] =3D IPRIO_DEFAULT_LOWER + 8, + [33] =3D IPRIO_DEFAULT_LOWER + 9, + [16] =3D IPRIO_DEFAULT_LOWER + 10, + [32] =3D IPRIO_DEFAULT_LOWER + 11, }; =20 uint8_t riscv_cpu_default_priority(int irq) @@ -1001,8 +1001,8 @@ restart: */ MemoryRegion *mr; hwaddr l =3D sizeof(target_ulong), addr1; - mr =3D address_space_translate(cs->as, pte_addr, - &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); + mr =3D address_space_translate(cs->as, pte_addr, &addr1, &= l, + false, MEMTXATTRS_UNSPECIFIED= ); if (memory_region_is_ram(mr)) { target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -1052,7 +1052,7 @@ restart: /* add write permission on stores or if the page is already di= rty, so that we TLB miss on later writes to update the dirty bit= */ if ((pte & PTE_W) && - (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { + (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { *prot |=3D PAGE_WRITE; } return TRANSLATE_SUCCESS; @@ -1281,9 +1281,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, false); =20 qemu_log_mask(CPU_LOG_MMU, - "%s 2nd-stage address=3D%" VADDR_PRIx " ret %d physica= l " - HWADDR_FMT_plx " prot %d\n", - __func__, im_address, ret, pa, prot2); + "%s 2nd-stage address=3D%" VADDR_PRIx + " ret %d physical " + HWADDR_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot2); =20 prot &=3D prot2; =20 @@ -1718,7 +1719,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->htval =3D htval; env->htinst =3D tinst; env->pc =3D (env->stvec >> 2 << 2) + - ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); } else { /* handle the trap in M-mode */ @@ -1749,7 +1750,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtval2 =3D mtval2; env->mtinst =3D tinst; env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); } =20 diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 449d236df6..5dd14d8390 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -248,8 +248,8 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float32_minnum(frs1, frs2, &env->fp_status) : - float32_minimum_number(frs1, frs2, &env->fp_status)); + float32_minnum(frs1, frs2, &env->fp_status) : + float32_minimum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) @@ -257,8 +257,8 @@ uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float32 frs1 =3D check_nanbox_s(env, rs1); float32 frs2 =3D check_nanbox_s(env, rs2); return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float32_maxnum(frs1, frs2, &env->fp_status) : - float32_maximum_number(frs1, frs2, &env->fp_status)); + float32_maxnum(frs1, frs2, &env->fp_status) : + float32_maximum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) @@ -361,15 +361,15 @@ uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t f= rs1, uint64_t frs2) uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { return env->priv_ver < PRIV_VERSION_1_11_0 ? - float64_minnum(frs1, frs2, &env->fp_status) : - float64_minimum_number(frs1, frs2, &env->fp_status); + float64_minnum(frs1, frs2, &env->fp_status) : + float64_minimum_number(frs1, frs2, &env->fp_status); } =20 uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) { return env->priv_ver < PRIV_VERSION_1_11_0 ? - float64_maxnum(frs1, frs2, &env->fp_status) : - float64_maximum_number(frs1, frs2, &env->fp_status); + float64_maxnum(frs1, frs2, &env->fp_status) : + float64_maximum_number(frs1, frs2, &env->fp_status); } =20 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) @@ -481,8 +481,8 @@ uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float16_minnum(frs1, frs2, &env->fp_status) : - float16_minimum_number(frs1, frs2, &env->fp_status)); + float16_minnum(frs1, frs2, &env->fp_status) : + float16_minimum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) @@ -490,8 +490,8 @@ uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1= , uint64_t rs2) float16 frs1 =3D check_nanbox_h(env, rs1); float16 frs2 =3D check_nanbox_h(env, rs2); return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? - float16_maxnum(frs1, frs2, &env->fp_status) : - float16_maximum_number(frs1, frs2, &env->fp_status)); + float16_maxnum(frs1, frs2, &env->fp_status) : + float16_maximum_number(frs1, frs2, &env->fp_statu= s)); } =20 uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index f2e3d38515..8e43bfc07c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -238,8 +238,8 @@ static bool vext_check_store(DisasContext *s, int vd, i= nt nf, uint8_t eew) { int8_t emul =3D eew - s->sew + s->lmul; return (emul >=3D -3 && emul <=3D 3) && - require_align(vd, emul) && - require_nf(vd, nf, emul); + require_align(vd, emul) && + require_nf(vd, nf, emul); } =20 /* @@ -315,7 +315,7 @@ static bool vext_check_ld_index(DisasContext *s, int vd= , int vs2, int8_t seg_vd; int8_t emul =3D eew - s->sew + s->lmul; bool ret =3D vext_check_st_index(s, vd, vs2, nf, eew) && - require_vm(vm, vd); + require_vm(vm, vd); =20 /* Each segment register group has to follow overlap rules. */ for (int i =3D 0; i < nf; ++i) { @@ -345,8 +345,8 @@ static bool vext_check_ld_index(DisasContext *s, int vd= , int vs2, static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm) { return require_vm(vm, vd) && - require_align(vd, s->lmul) && - require_align(vs, s->lmul); + require_align(vd, s->lmul) && + require_align(vs, s->lmul); } =20 /* @@ -365,7 +365,7 @@ static bool vext_check_ss(DisasContext *s, int vd, int = vs, int vm) static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_ss(s, vd, vs2, vm) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); } =20 static bool vext_check_ms(DisasContext *s, int vd, int vs) @@ -396,7 +396,7 @@ static bool vext_check_ms(DisasContext *s, int vd, int = vs) static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2) { bool ret =3D vext_check_ms(s, vd, vs2) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); if (vd !=3D vs1) { ret &=3D require_noover(vd, 0, vs1, s->lmul); } @@ -460,14 +460,14 @@ static bool vext_narrow_check_common(DisasContext *s,= int vd, int vs2, static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm) { return vext_wide_check_common(s, vd, vm) && - require_align(vs, s->lmul) && - require_noover(vd, s->lmul + 1, vs, s->lmul); + require_align(vs, s->lmul) && + require_noover(vd, s->lmul + 1, vs, s->lmul); } =20 static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm) { return vext_wide_check_common(s, vd, vm) && - require_align(vs, s->lmul + 1); + require_align(vs, s->lmul + 1); } =20 /* @@ -485,8 +485,8 @@ static bool vext_check_dd(DisasContext *s, int vd, int = vs, int vm) static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_ds(s, vd, vs2, vm) && - require_align(vs1, s->lmul) && - require_noover(vd, s->lmul + 1, vs1, s->lmul); + require_align(vs1, s->lmul) && + require_noover(vd, s->lmul + 1, vs1, s->lmul); } =20 /* @@ -507,7 +507,7 @@ static bool vext_check_dss(DisasContext *s, int vd, int= vs1, int vs2, int vm) static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_ds(s, vd, vs1, vm) && - require_align(vs2, s->lmul + 1); + require_align(vs2, s->lmul + 1); } =20 static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm) @@ -535,7 +535,7 @@ static bool vext_check_sd(DisasContext *s, int vd, int = vs, int vm) static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int = vm) { return vext_check_sd(s, vd, vs2, vm) && - require_align(vs1, s->lmul); + require_align(vs1, s->lmul); } =20 /* diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c index 7bf115b85e..e6a4f6120a 100644 --- a/target/riscv/m128_helper.c +++ b/target/riscv/m128_helper.c @@ -24,8 +24,8 @@ #include "exec/helper-proto.h" =20 target_ulong HELPER(divu_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong ql, qh; Int128 q; @@ -44,8 +44,8 @@ target_ulong HELPER(divu_i128)(CPURISCVState *env, } =20 target_ulong HELPER(remu_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong rl, rh; Int128 r; @@ -64,8 +64,8 @@ target_ulong HELPER(remu_i128)(CPURISCVState *env, } =20 target_ulong HELPER(divs_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong qh, ql; Int128 q; @@ -89,8 +89,8 @@ target_ulong HELPER(divs_i128)(CPURISCVState *env, } =20 target_ulong HELPER(rems_i128)(CPURISCVState *env, - target_ulong ul, target_ulong uh, - target_ulong vl, target_ulong vh) + target_ulong ul, target_ulong uh, + target_ulong vl, target_ulong vh) { target_ulong rh, rl; Int128 r; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8869346089..3ce2970785 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -136,15 +136,15 @@ static const VMStateDescription vmstate_vector =3D { .minimum_version_id =3D 2, .needed =3D vector_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64= ), - VMSTATE_UINTTL(env.vxrm, RISCVCPU), - VMSTATE_UINTTL(env.vxsat, RISCVCPU), - VMSTATE_UINTTL(env.vl, RISCVCPU), - VMSTATE_UINTTL(env.vstart, RISCVCPU), - VMSTATE_UINTTL(env.vtype, RISCVCPU), - VMSTATE_BOOL(env.vill, RISCVCPU), - VMSTATE_END_OF_LIST() - } + VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), + VMSTATE_UINTTL(env.vxrm, RISCVCPU), + VMSTATE_UINTTL(env.vxsat, RISCVCPU), + VMSTATE_UINTTL(env.vl, RISCVCPU), + VMSTATE_UINTTL(env.vstart, RISCVCPU), + VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_BOOL(env.vill, RISCVCPU), + VMSTATE_END_OF_LIST() + } }; =20 static bool pointermasking_needed(void *opaque) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c0c4ced7f0..ec9a384772 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -367,8 +367,8 @@ void helper_wfi(CPURISCVState *env) if (((prv_s || (!rvs && prv_u)) && get_field(env->mstatus, MSTATUS_TW)= ) || (rvs && prv_u && !env->virt_enabled)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } else if (env->virt_enabled && (prv_u || - (prv_s && get_field(env->hstatus, HSTATUS_VTW)))) { + } else if (env->virt_enabled && + (prv_u || (prv_s && get_field(env->hstatus, HSTATUS_VTW))))= { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { cs->halted =3D 1; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a08cd95658..3943b0f2e3 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -27,7 +27,7 @@ #include "exec/exec-all.h" =20 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, - uint8_t val); + uint8_t val); static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index); static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index); =20 @@ -220,8 +220,8 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_= index, target_ulong addr) { int result =3D 0; =20 - if ((addr >=3D env->pmp_state.addr[pmp_index].sa) - && (addr <=3D env->pmp_state.addr[pmp_index].ea)) { + if ((addr >=3D env->pmp_state.addr[pmp_index].sa) && + (addr <=3D env->pmp_state.addr[pmp_index].ea)) { result =3D 1; } else { result =3D 0; @@ -234,8 +234,9 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp_= index, target_ulong addr) * Check if the address has required RWX privs when no PMP entry is matche= d. */ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong ad= dr, - target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, - target_ulong mode) + target_ulong size, pmp_priv_t privs, + pmp_priv_t *allowed_privs, + target_ulong mode) { bool ret; =20 @@ -297,8 +298,8 @@ static bool pmp_hart_has_privs_default(CPURISCVState *e= nv, target_ulong addr, * Return negtive value if no match */ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, - target_ulong mode) + target_ulong size, pmp_priv_t privs, + pmp_priv_t *allowed_privs, target_ulong mode) { int i =3D 0; int ret =3D -1; @@ -466,7 +467,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong= addr, * Handle a write to a pmpcfg CSR */ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, - target_ulong val) + target_ulong val) { int i; uint8_t cfg_val; @@ -508,7 +509,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32= _t reg_index) * Handle a write to a pmpaddr CSR */ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, - target_ulong val) + target_ulong val) { trace_pmpaddr_csr_write(env->mhartid, addr_index, val); =20 diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index da32c61c85..b296ea1fc6 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -63,18 +63,19 @@ typedef struct { } pmp_table_t; =20 void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, - target_ulong val); + target_ulong val); target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); =20 void mseccfg_csr_write(CPURISCVState *env, target_ulong val); target_ulong mseccfg_csr_read(CPURISCVState *env); =20 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, - target_ulong val); + target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, - target_ulong mode); + target_ulong size, pmp_priv_t privs, + pmp_priv_t *allowed_privs, + target_ulong mode); target_ulong pmp_get_tlb_size(CPURISCVState *env, int pmp_index, target_ulong tlb_sa, target_ulong tlb_ea); void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 03748f72e6..3613aca28d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -746,8 +746,8 @@ EX_SH(12) } while (0) =20 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ - if (!ctx->cfg_ptr->ext_##A && \ - !ctx->cfg_ptr->ext_##B) { \ + if (!ctx->cfg_ptr->ext_##A && \ + !ctx->cfg_ptr->ext_##B) { \ return false; \ } \ } while (0) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2423affe37..6067b5cfc7 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -50,10 +50,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, } } =20 - if ((sew > cpu->cfg.elen) - || vill - || (ediv !=3D 0) - || (reserved !=3D 0)) { + if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { /* only set vill bit. */ env->vill =3D 1; env->vtype =3D 0; @@ -1116,7 +1113,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ \ *((ETYPE *)vd + H(i)) =3D DO_OP(s2, (ETYPE)(target_long)s1, carry)= ;\ } \ - env->vstart =3D 0; \ + env->vstart =3D 0; = \ /* set tail elements to 1s */ \ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } @@ -1308,7 +1305,8 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H= 8, DO_SRL, 0x3f) /* generate the helpers for shift instructions with one vector and one sca= lar */ #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ @@ -1735,9 +1733,9 @@ GEN_VEXT_VX(vmulhsu_vx_d, 8) /* Vector Integer Divide Instructions */ #define DO_DIVU(N, M) (unlikely(M =3D=3D 0) ? (__typeof(N))(-1) : N / M) #define DO_REMU(N, M) (unlikely(M =3D=3D 0) ? N : N % M) -#define DO_DIV(N, M) (unlikely(M =3D=3D 0) ? (__typeof(N))(-1) :\ +#define DO_DIV(N, M) (unlikely(M =3D=3D 0) ? (__typeof(N))(-1) : \ unlikely((N =3D=3D -N) && (M =3D=3D (__typeof(N))(-1))) ? N : N / = M) -#define DO_REM(N, M) (unlikely(M =3D=3D 0) ? N :\ +#define DO_REM(N, M) (unlikely(M =3D=3D 0) ? N : \ unlikely((N =3D=3D -N) && (M =3D=3D (__typeof(N))(-1))) ? 0 : N % = M) =20 RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU) @@ -1846,7 +1844,7 @@ GEN_VEXT_VX(vwmulsu_vx_h, 4) GEN_VEXT_VX(vwmulsu_vx_w, 8) =20 /* Vector Single-Width Integer Multiply-Add Instructions */ -#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ { \ TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ @@ -2277,7 +2275,8 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void= *vs2, /* generate helpers for fixed point instructions with OPIVX format */ #define GEN_VEXT_VX_RM(NAME, ESZ) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ { \ vext_vx_rm_2(vd, v0, s1, vs2, env, desc, \ do_##NAME, ESZ); \ @@ -2651,7 +2650,7 @@ static inline int8_t vsmul8(CPURISCVState *env, int v= xrm, int8_t a, int8_t b) =20 res =3D (int16_t)a * (int16_t)b; round =3D get_round(vxrm, res, 7); - res =3D (res >> 7) + round; + res =3D (res >> 7) + round; =20 if (res > INT8_MAX) { env->vxsat =3D 0x1; @@ -2671,7 +2670,7 @@ static int16_t vsmul16(CPURISCVState *env, int vxrm, = int16_t a, int16_t b) =20 res =3D (int32_t)a * (int32_t)b; round =3D get_round(vxrm, res, 15); - res =3D (res >> 15) + round; + res =3D (res >> 15) + round; =20 if (res > INT16_MAX) { env->vxsat =3D 0x1; @@ -2691,7 +2690,7 @@ static int32_t vsmul32(CPURISCVState *env, int vxrm, = int32_t a, int32_t b) =20 res =3D (int64_t)a * (int64_t)b; round =3D get_round(vxrm, res, 31); - res =3D (res >> 31) + round; + res =3D (res >> 31) + round; =20 if (res > INT32_MAX) { env->vxsat =3D 0x1; @@ -2758,7 +2757,7 @@ vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8= _t b) uint8_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; return res; } static inline uint16_t @@ -2862,7 +2861,7 @@ vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8= _t b) int16_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > INT8_MAX) { env->vxsat =3D 0x1; return INT8_MAX; @@ -2881,7 +2880,7 @@ vnclip16(CPURISCVState *env, int vxrm, int32_t a, int= 16_t b) int32_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > INT16_MAX) { env->vxsat =3D 0x1; return INT16_MAX; @@ -2900,7 +2899,7 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int= 32_t b) int64_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > INT32_MAX) { env->vxsat =3D 0x1; return INT32_MAX; @@ -2933,7 +2932,7 @@ vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, ui= nt8_t b) uint16_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > UINT8_MAX) { env->vxsat =3D 0x1; return UINT8_MAX; @@ -2949,7 +2948,7 @@ vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, u= int16_t b) uint32_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > UINT16_MAX) { env->vxsat =3D 0x1; return UINT16_MAX; @@ -2965,7 +2964,7 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, u= int32_t b) uint64_t res; =20 round =3D get_round(vxrm, a, shift); - res =3D (a >> shift) + round; + res =3D (a >> shift) + round; if (res > UINT32_MAX) { env->vxsat =3D 0x1; return UINT32_MAX; @@ -3052,7 +3051,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ + vext_get_total_elems(env, desc, ESZ); \ uint32_t vta =3D vext_vta(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -3118,13 +3117,13 @@ GEN_VEXT_VF(vfrsub_vf_d, 8) static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s) { return float32_add(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), s); + float16_to_float32(b, true, s), s); } =20 static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s) { return float64_add(float32_to_float64(a, s), - float32_to_float64(b, s), s); + float32_to_float64(b, s), s); =20 } =20 @@ -3140,13 +3139,13 @@ GEN_VEXT_VF(vfwadd_vf_w, 8) static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s) { return float32_sub(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), s); + float16_to_float32(b, true, s), s); } =20 static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s) { return float64_sub(float32_to_float64(a, s), - float32_to_float64(b, s), s); + float32_to_float64(b, s), s); =20 } =20 @@ -3250,13 +3249,13 @@ GEN_VEXT_VF(vfrdiv_vf_d, 8) static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s) { return float32_mul(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), s); + float16_to_float32(b, true, s), s); } =20 static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s) { return float64_mul(float32_to_float64(a, s), - float32_to_float64(b, s), s); + float32_to_float64(b, s), s); =20 } RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16) @@ -3271,7 +3270,7 @@ GEN_VEXT_VF(vfwmul_vf_w, 8) /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ - CPURISCVState *env) \ + CPURISCVState *env) \ { \ TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ @@ -3303,7 +3302,7 @@ GEN_VEXT_VV_ENV(vfmacc_vv_d, 8) =20 #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ - CPURISCVState *env) \ + CPURISCVState *env) \ { \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ TD d =3D *((TD *)vd + HD(i)); \ @@ -3319,20 +3318,20 @@ GEN_VEXT_VF(vfmacc_vf_d, 8) =20 static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { - return float16_muladd(a, b, d, - float_muladd_negate_c | float_muladd_negate_product, s); + return float16_muladd(a, b, d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status = *s) { - return float32_muladd(a, b, d, - float_muladd_negate_c | float_muladd_negate_product, s); + return float32_muladd(a, b, d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status = *s) { - return float64_muladd(a, b, d, - float_muladd_negate_c | float_muladd_negate_product, s); + return float64_muladd(a, b, d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16) @@ -3434,20 +3433,20 @@ GEN_VEXT_VF(vfmadd_vf_d, 8) =20 static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { - return float16_muladd(d, b, a, - float_muladd_negate_c | float_muladd_negate_product, s); + return float16_muladd(d, b, a, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status = *s) { - return float32_muladd(d, b, a, - float_muladd_negate_c | float_muladd_negate_product, s); + return float32_muladd(d, b, a, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status = *s) { - return float64_muladd(d, b, a, - float_muladd_negate_c | float_muladd_negate_product, s); + return float64_muladd(d, b, a, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16) @@ -3523,13 +3522,13 @@ GEN_VEXT_VF(vfnmsub_vf_d, 8) static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status = *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, 0, s); + float16_to_float32(b, true, s), d, 0, s); } =20 static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status = *s) { return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, 0, s); + float32_to_float64(b, s), d, 0, s); } =20 RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16) @@ -3544,15 +3543,16 @@ GEN_VEXT_VF(vfwmacc_vf_w, 8) static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status= *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, - float_muladd_negate_c | float_muladd_negate_produc= t, s); + float16_to_float32(b, true, s), d, + float_muladd_negate_c | float_muladd_negate_prod= uct, + s); } =20 static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status= *s) { - return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, - float_muladd_negate_c | float_muladd_negate_produc= t, s); + return float64_muladd(float32_to_float64(a, s), float32_to_float64(b, = s), + d, float_muladd_negate_c | + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) @@ -3567,15 +3567,15 @@ GEN_VEXT_VF(vfwnmacc_vf_w, 8) static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status = *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, - float_muladd_negate_c, s); + float16_to_float32(b, true, s), d, + float_muladd_negate_c, s); } =20 static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status = *s) { return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, - float_muladd_negate_c, s); + float32_to_float64(b, s), d, + float_muladd_negate_c, s); } =20 RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16) @@ -3590,15 +3590,15 @@ GEN_VEXT_VF(vfwmsac_vf_w, 8) static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status= *s) { return float32_muladd(float16_to_float32(a, true, s), - float16_to_float32(b, true, s), d, - float_muladd_negate_product, s); + float16_to_float32(b, true, s), d, + float_muladd_negate_product, s); } =20 static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status= *s) { return float64_muladd(float32_to_float64(a, s), - float32_to_float64(b, s), d, - float_muladd_negate_product, s); + float32_to_float64(b, s), d, + float_muladd_negate_product, s); } =20 RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16) @@ -3616,9 +3616,9 @@ GEN_VEXT_VF(vfwnmsac_vf_w, 8) #define OP_UU_W uint32_t, uint32_t, uint32_t #define OP_UU_D uint64_t, uint64_t, uint64_t =20 -#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i, \ - CPURISCVState *env) \ + CPURISCVState *env) \ { \ TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ *((TD *)vd + HD(i)) =3D OP(s2, &env->fp_status); \ @@ -3626,7 +3626,7 @@ static void do_##NAME(void *vd, void *vs2, int i, = \ =20 #define GEN_VEXT_V_ENV(NAME, ESZ) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ + CPURISCVState *env, uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ @@ -3703,9 +3703,9 @@ static uint64_t frsqrt7(uint64_t f, int exp_size, int= frac_size) } =20 int idx =3D ((exp & 1) << (precision - 1)) | - (frac >> (frac_size - precision + 1)); + (frac >> (frac_size - precision + 1)); uint64_t out_frac =3D (uint64_t)(lookup_table[idx]) << - (frac_size - precision); + (frac_size - precision); uint64_t out_exp =3D (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2; =20 uint64_t val =3D 0; @@ -3727,9 +3727,9 @@ static float16 frsqrt7_h(float16 f, float_status *s) * frsqrt7(-subnormal) =3D canonical NaN */ if (float16_is_signaling_nan(f, s) || - (float16_is_infinity(f) && sign) || - (float16_is_normal(f) && sign) || - (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign= )) { + (float16_is_infinity(f) && sign) || + (float16_is_normal(f) && sign) || + (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) { s->float_exception_flags |=3D float_flag_invalid; return float16_default_nan(s); } @@ -3767,9 +3767,9 @@ static float32 frsqrt7_s(float32 f, float_status *s) * frsqrt7(-subnormal) =3D canonical NaN */ if (float32_is_signaling_nan(f, s) || - (float32_is_infinity(f) && sign) || - (float32_is_normal(f) && sign) || - (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign= )) { + (float32_is_infinity(f) && sign) || + (float32_is_normal(f) && sign) || + (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) { s->float_exception_flags |=3D float_flag_invalid; return float32_default_nan(s); } @@ -3807,9 +3807,9 @@ static float64 frsqrt7_d(float64 f, float_status *s) * frsqrt7(-subnormal) =3D canonical NaN */ if (float64_is_signaling_nan(f, s) || - (float64_is_infinity(f) && sign) || - (float64_is_normal(f) && sign) || - (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign= )) { + (float64_is_infinity(f) && sign) || + (float64_is_normal(f) && sign) || + (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) { s->float_exception_flags |=3D float_flag_invalid; return float64_default_nan(s); } @@ -3897,18 +3897,18 @@ static uint64_t frec7(uint64_t f, int exp_size, int= frac_size, ((s->float_rounding_mode =3D=3D float_round_up) && sign)) { /* Return greatest/negative finite value. */ return (sign << (exp_size + frac_size)) | - (MAKE_64BIT_MASK(frac_size, exp_size) - 1); + (MAKE_64BIT_MASK(frac_size, exp_size) - 1); } else { /* Return +-inf. */ return (sign << (exp_size + frac_size)) | - MAKE_64BIT_MASK(frac_size, exp_size); + MAKE_64BIT_MASK(frac_size, exp_size); } } } =20 int idx =3D frac >> (frac_size - precision); uint64_t out_frac =3D (uint64_t)(lookup_table[idx]) << - (frac_size - precision); + (frac_size - precision); uint64_t out_exp =3D 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp; =20 if (out_exp =3D=3D 0 || out_exp =3D=3D UINT64_MAX) { @@ -4422,8 +4422,8 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ - *((ETYPE *)vd + H(i)) \ - =3D (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ + *((ETYPE *)vd + H(i)) =3D \ + (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ } \ env->vstart =3D 0; \ /* set tail elements to 1s */ \ @@ -4564,7 +4564,8 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) /* Vector Single-Width Integer Reduction Instructions */ #define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, uint32_t desc) \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ @@ -5013,7 +5014,8 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) =20 #define GEN_VEXT_VSLIE1UP(BITWIDTH, H) = \ static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, = \ - void *vs2, CPURISCVState *env, uint32_t desc) = \ + void *vs2, CPURISCVState *env, = \ + uint32_t desc) = \ { = \ typedef uint##BITWIDTH##_t ETYPE; = \ uint32_t vm =3D vext_vm(desc); = \ @@ -5061,7 +5063,8 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64) =20 #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) = \ static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, = \ - void *vs2, CPURISCVState *env, uint32_t desc) = \ + void *vs2, CPURISCVState *env, = \ + uint32_t desc) = \ { = \ typedef uint##BITWIDTH##_t ETYPE; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1680685228949100003 Content-Type: text/plain; charset="utf-8" Fix formats for multi-lines comments. Add spaces around single line comments(after "/*" and before "*/"). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/arch_dump.c | 3 +- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 26 ++++---- target/riscv/cpu_bits.h | 2 +- target/riscv/cpu_helper.c | 57 +++++++++++------ target/riscv/csr.c | 6 +- target/riscv/insn_trans/trans_rvv.c.inc | 8 ++- target/riscv/pmp.c | 41 +++++++------ target/riscv/sbi_ecall_interface.h | 8 +-- target/riscv/translate.c | 20 +++--- target/riscv/vector_helper.c | 82 +++++++++++++++---------- 11 files changed, 151 insertions(+), 104 deletions(-) diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 573587810e..434c8a3dbb 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -1,4 +1,5 @@ -/* Support for writing ELF notes for RISC-V architectures +/* + * Support for writing ELF notes for RISC-V architectures * * Copyright (C) 2021 Huawei Technologies Co., Ltd * diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8ed8601399..2e45b1f076 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -56,7 +56,7 @@ struct isa_ext_data { #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} =20 -/** +/* * Here are the ordering rules of extension naming defined by RISC-V * specification : * 1. All extensions should be separated from other multi-letter extensions diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 995192757a..5018a3b1b2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -124,7 +124,7 @@ FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 1= 1) typedef struct PMUCTRState { /* Current value of a counter */ target_ulong mhpmcounter_val; - /* Current value of a counter in RV32*/ + /* Current value of a counter in RV32 */ target_ulong mhpmcounterh_val; /* Snapshot values of counter */ target_ulong mhpmcounter_prev; @@ -280,8 +280,10 @@ struct CPUArchState { target_ulong satp_hs; uint64_t mstatus_hs; =20 - /* Signals whether the current exception occurred with two-stage addre= ss - translation active. */ + /* + * Signals whether the current exception occurred with two-stage addre= ss + * translation active. + */ bool two_stage_lookup; /* * Signals whether the current exception occurred while doing two-stage @@ -297,10 +299,10 @@ struct CPUArchState { /* PMU counter state */ PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; =20 - /* PMU event selector configured values. First three are unused*/ + /* PMU event selector configured values. First three are unused */ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; =20 - /* PMU event selector configured values for RV32*/ + /* PMU event selector configured values for RV32 */ target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; =20 target_ulong sscratch; @@ -389,7 +391,7 @@ struct CPUArchState { =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) =20 -/** +/* * RISCVCPUClass: * @parent_realize: The parent class' realize handler. * @parent_phases: The parent class' reset phase handlers. @@ -397,9 +399,9 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_= CPU) * A RISCV CPU model. */ struct RISCVCPUClass { - /*< private >*/ + /* < private > */ CPUClass parent_class; - /*< public >*/ + /* < public > */ DeviceRealize parent_realize; ResettablePhases parent_phases; }; @@ -530,16 +532,16 @@ struct RISCVCPUConfig { =20 typedef struct RISCVCPUConfig RISCVCPUConfig; =20 -/** +/* * RISCVCPU: * @env: #CPURISCVState * * A RISCV CPU. */ struct ArchCPU { - /*< private >*/ + /* < private > */ CPUState parent_obj; - /*< public >*/ + /* < public > */ CPUNegativeOffsetState neg; CPURISCVState env; =20 @@ -813,7 +815,7 @@ enum { CSR_TABLE_SIZE =3D 0x1000 }; =20 -/** +/* * The event id are encoded based on the encoding specified in the * SBI specification v0.3 */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 190e517862..101702cb4a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -731,7 +731,7 @@ typedef enum RISCVException { #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) =20 -/* General PointerMasking CSR bits*/ +/* General PointerMasking CSR bits */ #define PM_ENABLE 0x00000001ULL #define PM_CURRENT 0x00000002ULL #define PM_INSN 0x00000004ULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8d2547a164..445ffe691a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -717,7 +717,8 @@ static int get_physical_address_pmp(CPURISCVState *env,= int *prot, return TRANSLATE_SUCCESS; } =20 -/* get_physical_address - get the physical address for this virtual address +/* + * get_physical_address - get the physical address for this virtual address * * Do a page table walk to obtain the physical address corresponding to a * virtual address. Returns 0 if the translation was successful @@ -745,9 +746,11 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, bool first_stage, bool two_stage, bool is_debug) { - /* NOTE: the env->pc value visible here will not be + /* + * NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler - * (riscv_cpu_do_interrupt) is correct */ + * (riscv_cpu_do_interrupt) is correct + */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; @@ -767,8 +770,10 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, use_background =3D true; } =20 - /* MPRV does not affect the virtual-machine load/store - instructions, HLV, HLVX, and HSV. */ + /* + * MPRV does not affect the virtual-machine load/store + * instructions, HLV, HLVX, and HSV. + */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { @@ -778,8 +783,10 @@ static int get_physical_address(CPURISCVState *env, hw= addr *physical, } =20 if (first_stage =3D=3D false) { - /* We are in stage 2 translation, this is similar to stage 1. */ - /* Stage 2 is always taken as U-mode */ + /* + * We are in stage 2 translation, this is similar to stage 1. + * Stage 2 is always taken as U-mode + */ mode =3D PRV_U; } =20 @@ -1007,8 +1014,10 @@ restart: target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1); #if TCG_OVERSIZED_GUEST - /* MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic */ + /* + * MTTCG is not enabled on oversized TCG guests so + * page table updates do not need to be atomic + */ *pte_pa =3D pte =3D updated_pte; #else target_ulong old_pte =3D @@ -1020,14 +1029,18 @@ restart: } #endif } else { - /* misconfigured PTE in ROM (AD bits are not preset) or - * PTE is in IO space and can't be updated atomically = */ + /* + * misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically + */ return TRANSLATE_FAIL; } } =20 - /* for superpage mappings, make a fake leaf PTE for the TLB's - benefit. */ + /* + * for superpage mappings, make a fake leaf PTE for the TLB's + * benefit. + */ target_ulong vpn =3D addr >> PGSHIFT; =20 if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { @@ -1049,8 +1062,10 @@ restart: if (pte & PTE_X) { *prot |=3D PAGE_EXEC; } - /* add write permission on stores or if the page is already di= rty, - so that we TLB miss on later writes to update the dirty bit= */ + /* + * add write permission on stores or if the page is already di= rty, + * so that we TLB miss on later writes to update the dirty bit + */ if ((pte & PTE_W) && (access_type =3D=3D MMU_DATA_STORE || (pte & PTE_D))) { *prot |=3D PAGE_WRITE; @@ -1235,8 +1250,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - /* MPRV does not affect the virtual-machine load/store - instructions, HLV, HLVX, and HSV. */ + /* + * MPRV does not affect the virtual-machine load/store + * instructions, HLV, HLVX, and HSV. + */ if (riscv_cpu_two_stage_lookup(mmu_idx)) { mode =3D get_field(env->hstatus, HSTATUS_SPVP); } else if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && @@ -1577,7 +1594,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool write_gva =3D false; uint64_t s; =20 - /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide + /* + * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. */ bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); @@ -1754,7 +1772,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_mode(env, PRV_M); } =20 - /* NOTE: it is not necessary to yield load reservations here. It is on= ly + /* + * NOTE: it is not necessary to yield load reservations here. It is on= ly * necessary for an SC from "another hart" to cause a load reservation * to be yielded. Refer to the memory consistency model section of the * RISC-V ISA Specification. diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 41e56012d5..76755ee128 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -189,7 +189,7 @@ static RISCVException mctr(CPURISCVState *env, int csrn= o) } ctr_index =3D csrno - base_csrno; if (!pmu_num || ctr_index >=3D pmu_num) { - /* The PMU is not enabled or counter is out of range*/ + /* The PMU is not enabled or counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -877,7 +877,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, counter.mhpmcounter_val; =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { - /** + /* * Counter should not increment if inhibit bit is set. We can't re= ally * stop the icount counting. Just return the counter value written= by * the supervisor to indicate that counter was not incremented. @@ -891,7 +891,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, } } =20 - /** + /* * The kernel computes the perf delta by subtracting the current value= from * the value it initialized previously (ctr_val). */ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 8e43bfc07c..ca3c4c1a3d 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3136,9 +3136,11 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr = *a) return false; } =20 -/* vmsbf.m set-before-first mask bit */ -/* vmsif.m set-includ-first mask bit */ -/* vmsof.m set-only-first mask bit */ +/* + * vmsbf.m set-before-first mask bit + * vmsif.m set-including-first mask bit + * vmsof.m set-only-first mask bit + */ #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 3943b0f2e3..6ab2ae81c7 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -132,15 +132,15 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_= t pmp_index, uint8_t val) static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulon= g *ea) { /* - aaaa...aaa0 8-byte NAPOT range - aaaa...aa01 16-byte NAPOT range - aaaa...a011 32-byte NAPOT range - ... - aa01...1111 2^XLEN-byte NAPOT range - a011...1111 2^(XLEN+1)-byte NAPOT range - 0111...1111 2^(XLEN+2)-byte NAPOT range - 1111...1111 Reserved - */ + * aaaa...aaa0 8-byte NAPOT range + * aaaa...aa01 16-byte NAPOT range + * aaaa...a011 32-byte NAPOT range + * ... + * aa01...1111 2^XLEN-byte NAPOT range + * a011...1111 2^(XLEN+1)-byte NAPOT range + * 0111...1111 2^(XLEN+2)-byte NAPOT range + * 1111...1111 Reserved + */ a =3D (a << 2) | 0x3; *sa =3D a & (a + 1); *ea =3D a | (a + 1); @@ -205,7 +205,8 @@ void pmp_update_rule_nums(CPURISCVState *env) } } =20 -/* Convert cfg/addr reg values here into simple 'sa' --> start address and= 'ea' +/* + * Convert cfg/addr reg values here into simple 'sa' --> start address and= 'ea' * end address values. * This function is called relatively infrequently whereas the check that * an address is within a pmp rule is called often, so optimise that one @@ -329,8 +330,10 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulon= g addr, pmp_size =3D size; } =20 - /* 1.10 draft priv spec states there is an implicit order - from low to high */ + /* + * 1.10 draft priv spec states there is an implicit order + * from low to high + */ for (i =3D 0; i < MAX_RISCV_PMPS; i++) { s =3D pmp_is_in_range(env, i, addr); e =3D pmp_is_in_range(env, i, addr + pmp_size - 1); @@ -609,13 +612,13 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, int= pmp_index, return TARGET_PAGE_SIZE; } else { /* - * At this point we have a tlb_size that is the smallest possible s= ize - * That fits within a TARGET_PAGE_SIZE and the PMP region. - * - * If the size is less then TARGET_PAGE_SIZE we drop the size to 1. - * This means the result isn't cached in the TLB and is only used f= or - * a single translation. - */ + * At this point we have a tlb_size that is the smallest possible = size + * That fits within a TARGET_PAGE_SIZE and the PMP region. + * + * If the size is less then TARGET_PAGE_SIZE we drop the size to 1. + * This means the result isn't cached in the TLB and is only used = for + * a single translation. + */ return 1; } } diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_in= terface.h index 77574ed4cb..43899d08f6 100644 --- a/target/riscv/sbi_ecall_interface.h +++ b/target/riscv/sbi_ecall_interface.h @@ -28,7 +28,7 @@ #define SBI_EXT_RFENCE 0x52464E43 #define SBI_EXT_HSM 0x48534D =20 -/* SBI function IDs for BASE extension*/ +/* SBI function IDs for BASE extension */ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 #define SBI_EXT_BASE_GET_IMP_ID 0x1 #define SBI_EXT_BASE_GET_IMP_VERSION 0x2 @@ -37,13 +37,13 @@ #define SBI_EXT_BASE_GET_MARCHID 0x5 #define SBI_EXT_BASE_GET_MIMPID 0x6 =20 -/* SBI function IDs for TIME extension*/ +/* SBI function IDs for TIME extension */ #define SBI_EXT_TIME_SET_TIMER 0x0 =20 -/* SBI function IDs for IPI extension*/ +/* SBI function IDs for IPI extension */ #define SBI_EXT_IPI_SEND_IPI 0x0 =20 -/* SBI function IDs for RFENCE extension*/ +/* SBI function IDs for RFENCE extension */ #define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1 #define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3613aca28d..d0094922b6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -69,11 +69,13 @@ typedef struct DisasContext { uint32_t mstatus_hs_fs; uint32_t mstatus_hs_vs; uint32_t mem_idx; - /* Remember the rounding mode encoded in the previous fp instruction, - which we have already installed into env->fp_status. Or -1 for - no previous fp instruction. Note that we exit the TB when writing - to any system register, which includes CSR_FRM, so we do not have - to reset this known value. */ + /* + * Remember the rounding mode encoded in the previous fp instruction, + * which we have already installed into env->fp_status. Or -1 for + * no previous fp instruction. Note that we exit the TB when writing + * to any system register, which includes CSR_FRM, so we do not have + * to reset this known value. + */ int frm; RISCVMXL ol; bool virt_inst_excp; @@ -491,7 +493,7 @@ static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) } } =20 -/* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ +/* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) { if (!ctx->cfg_ptr->ext_zfinx) { @@ -598,7 +600,8 @@ static TCGv get_address_indexed(DisasContext *ctx, int = rs1, TCGv offs) } =20 #ifndef CONFIG_USER_ONLY -/* The states of mstatus_fs are: +/* + * The states of mstatus_fs are: * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. @@ -636,7 +639,8 @@ static inline void mark_fs_dirty(DisasContext *ctx) { } #endif =20 #ifndef CONFIG_USER_ONLY -/* The states of mstatus_vs are: +/* + * The states of mstatus_vs are: * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty * We will have already diagnosed disabled state, * and need to turn initial/clean into dirty. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 6067b5cfc7..81ac85b7d5 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -287,7 +287,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, = target_ulong vl, } =20 /* - *** stride: access vector element from strided memory + * stride: access vector element from strided memory */ static void vext_ldst_stride(void *vd, void *v0, target_ulong base, @@ -353,10 +353,10 @@ GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w) GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) =20 /* - *** unit-stride: access elements stored contiguously in memory + * unit-stride: access elements stored contiguously in memory */ =20 -/* unmasked unit-stride load and store operation*/ +/* unmasked unit-stride load and store operation */ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t des= c, vext_ldst_elem_fn *ldst_elem, uint32_t log2_esz, uint32_t evl, @@ -429,7 +429,7 @@ GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) =20 /* - *** unit stride mask load and store, EEW =3D 1 + * unit stride mask load and store, EEW =3D 1 */ void HELPER(vlm_v)(void *vd, void *v0, target_ulong base, CPURISCVState *env, uint32_t desc) @@ -450,7 +450,7 @@ void HELPER(vsm_v)(void *vd, void *v0, target_ulong bas= e, } =20 /* - *** index: access vector element from indexed memory + * index: access vector element from indexed memory */ typedef target_ulong vext_get_index_addr(target_ulong base, uint32_t idx, void *vs2); @@ -554,7 +554,7 @@ GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w) GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d) =20 /* - *** unit-stride fault-only-fisrt load instructions + * unit-stride fault-only-fisrt load instructions */ static inline void vext_ldff(void *vd, void *v0, target_ulong base, @@ -571,7 +571,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t vma =3D vext_vma(desc); target_ulong addr, offset, remain; =20 - /* probe every access*/ + /* probe every access */ for (i =3D env->vstart; i < env->vl; i++) { if (!vm && !vext_elem_mask(v0, i)) { continue; @@ -660,7 +660,7 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d) #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) =20 /* - *** load and store whole register instructions + * load and store whole register instructions */ static void vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t = desc, @@ -733,7 +733,7 @@ GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b) GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) =20 /* - *** Vector Integer Arithmetic Instructions + * Vector Integer Arithmetic Instructions */ =20 /* expand macro args before macro */ @@ -1149,8 +1149,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, voi= d *vs2, \ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -1185,8 +1187,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s= 1, \ DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -1392,8 +1396,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, voi= d *vs2, \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -1455,8 +1461,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s= 1, void *vs2, \ DO_OP(s2, (ETYPE)(target_long)s1)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -2075,7 +2083,7 @@ GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4) GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8) =20 /* - *** Vector Fixed-Point Arithmetic Instructions + * Vector Fixed-Point Arithmetic Instructions */ =20 /* Vector Single-Width Saturating Add and Subtract */ @@ -2988,7 +2996,7 @@ GEN_VEXT_VX_RM(vnclipu_wx_h, 2) GEN_VEXT_VX_RM(vnclipu_wx_w, 4) =20 /* - *** Vector Float Point Arithmetic Instructions + * Vector Float Point Arithmetic Instructions */ /* Vector Single-Width Floating-Point Add/Subtract Instructions */ #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ @@ -4171,8 +4179,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, voi= d *vs2, \ DO_OP(s2, s1, &env->fp_status)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -4208,8 +4218,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, v= oid *vs2, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail-agnostic */ \ - /* set tail elements to 1s */ \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -4472,7 +4484,9 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8) #define WOP_UU_B uint16_t, uint8_t, uint8_t #define WOP_UU_H uint32_t, uint16_t, uint16_t #define WOP_UU_W uint64_t, uint32_t, uint32_t -/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned inte= ger.*/ +/* + * vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned inte= ger. + */ RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32) RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64) GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 4) @@ -4559,7 +4573,7 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2) GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) =20 /* - *** Vector Reduction Operations + * Vector Reduction Operations */ /* Vector Single-Width Integer Reduction Instructions */ #define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ @@ -4713,7 +4727,7 @@ GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4= , H2, fwadd16) GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) =20 /* - *** Vector Mask Operations + * Vector Mask Operations */ /* Vector Mask-Register Logical Instructions */ #define GEN_VEXT_MASK_VV(NAME, OP) \ @@ -4733,10 +4747,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ vext_set_elem_mask(vd, i, OP(b, a)); \ } \ env->vstart =3D 0; \ - /* mask destination register are always tail- \ - * agnostic \ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s */ \ - /* set tail elements to 1s */ \ if (vta_all_1s) { \ for (; i < total_elems; i++) { \ vext_set_elem_mask(vd, i, 1); \ @@ -4779,7 +4793,7 @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPU= RISCVState *env, return cnt; } =20 -/* vfirst find-first-set mask bit*/ +/* vfirst find-first-set mask bit */ target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env, uint32_t desc) { @@ -4844,8 +4858,10 @@ static void vmsetm(void *vd, void *v0, void *vs2, CP= URISCVState *env, } } env->vstart =3D 0; - /* mask destination register are always tail-agnostic */ - /* set tail elements to 1s */ + /* + * mask destination register are always tail-agnostic + * set tail elements to 1s + */ if (vta_all_1s) { for (; i < total_elems; i++) { vext_set_elem_mask(vd, i, 1); @@ -4937,7 +4953,7 @@ GEN_VEXT_VID_V(vid_v_w, uint32_t, H4) GEN_VEXT_VID_V(vid_v_d, uint64_t, H8) =20 /* - *** Vector Permutation Instructions + * Vector Permutation Instructions */ =20 /* Vector Slide Instructions */ --=20 2.25.1 From nobody Sat May 18 20:15:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 05 Apr 2023 16:58:20 +0800 (CST) From: Weiwei Li To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v3 4/4] target/riscv: Fix lines with over 80 characters Date: Wed, 5 Apr 2023 16:58:13 +0800 Message-Id: <20230405085813.40643-5-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230405085813.40643-1-liweiwei@iscas.ac.cn> References: <20230405085813.40643-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowAAH+BQoOC1kWY5GDg--.24854S6 X-Coremail-Antispam: 1UD129KBjvAXoW3ur1xAry8Ar18XFy5GFyfJFb_yoW8CFWrZo WrGr4rZrWkCw1S9asI9F1Iqr17Xr4Dtws5Xa1DKFW0g3Z3WrWrXFW3trZxAay2qrs3AFWU Xa92qF15JF1kAryfn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUO07AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j 6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x0262 8vn2kIc2xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GF ylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxV WUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU OBTYUUUUU X-Originating-IP: [180.175.29.170] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1680685188738100001 Content-Type: text/plain; charset="utf-8" Fix lines with over 80 characters for both code and comments. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 +- target/riscv/cpu.h | 4 +- target/riscv/cpu_helper.c | 3 +- target/riscv/csr.c | 38 ++++++++++-------- target/riscv/debug.c | 11 +++--- target/riscv/gdbstub.c | 3 +- target/riscv/pmp.c | 6 ++- target/riscv/pmu.c | 3 +- target/riscv/vector_helper.c | 76 ++++++++++++++++++++++++------------ 9 files changed, 91 insertions(+), 56 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2e45b1f076..cb68916fce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1700,7 +1700,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) device_class_set_props(dc, riscv_cpu_properties); } =20 -static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, + int max_str_len) { char *old =3D *isa_str; char *new =3D *isa_str; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5018a3b1b2..cbf3de2708 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -591,8 +591,8 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, = int mmu_idx, - uintptr_t retaddr); + MMUAccessType access_type, + int mmu_idx, uintptr_t reta= ddr); bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 445ffe691a..2310c7905f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1121,7 +1121,8 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; } else { cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_= FAULT; + RISCV_EXCP_STORE_PAGE_FAULT : + RISCV_EXCP_STORE_AMO_ACCESS_FAULT; } break; default: diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 76755ee128..e0b871f6dc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1137,7 +1137,8 @@ static const target_ulong sstatus_v1_10_mask =3D SSTA= TUS_SIE | SSTATUS_SPIE | static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | SIP_LCOFIP; static const target_ulong hip_writable_mask =3D MIP_VSSIP; -static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | M= IP_VSEIP; +static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | + MIP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; =20 const bool valid_vm_1_10_32[16] =3D { @@ -1298,7 +1299,8 @@ static RISCVException write_mstatush(CPURISCVState *e= nv, int csrno, static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno, Int128 *val) { - *val =3D int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->ms= tatus)); + *val =3D int128_make128(env->mstatus, add_status_sd(MXL_RV128, + env->mstatus)); return RISCV_EXCP_NONE; } =20 @@ -2823,7 +2825,8 @@ static RISCVException write_hstatus(CPURISCVState *en= v, int csrno, { env->hstatus =3D val; if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { - qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); + qemu_log_mask(LOG_UNIMP, + "QEMU does not support mixed HSXLEN options."); } if (get_field(val, HSTATUS_VSBE) !=3D 0) { qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.= "); @@ -3490,9 +3493,9 @@ static RISCVException write_mmte(CPURISCVState *env, = int csrno, target_ulong wpri_val =3D val & MMTE_MASK; =20 if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT= _lx "\n", - "MMTE: WPRI violation written 0x", val, - "vs expected 0x", wpri_val); + qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" + TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x= ", + val, "vs expected 0x", wpri_val); } /* for machine mode pm.current is hardwired to 1 */ wpri_val |=3D MMTE_M_PM_CURRENT; @@ -3521,9 +3524,9 @@ static RISCVException write_smte(CPURISCVState *env, = int csrno, target_ulong wpri_val =3D val & SMTE_MASK; =20 if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT= _lx "\n", - "SMTE: WPRI violation written 0x", val, - "vs expected 0x", wpri_val); + qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" + TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x= ", + val, "vs expected 0x", wpri_val); } =20 /* if pm.current=3D=3D0 we can't modify current PM CSRs */ @@ -3549,9 +3552,9 @@ static RISCVException write_umte(CPURISCVState *env, = int csrno, target_ulong wpri_val =3D val & UMTE_MASK; =20 if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT= _lx "\n", - "UMTE: WPRI violation written 0x", val, - "vs expected 0x", wpri_val); + qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" + TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x= ", + val, "vs expected 0x", wpri_val); } =20 if (check_pm_current_disabled(env, csrno)) { @@ -3941,7 +3944,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, * Fall back to 64-bit version for now, if the 128-bit alternative isn= 't * at all defined. * Note, some CSRs don't need to extend to MXLEN (64 upper bits non - * significant), for those, this fallback is correctly handling the ac= cesses + * significant), for those, this fallback is correctly handling the + * accesses */ target_ulong old_value; ret =3D riscv_csrrw_do64(env, csrno, &old_value, @@ -4154,11 +4158,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, - NULL, read_sstatus_i128 = }, - [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, - [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, + NULL, read_sstatus_i128 = }, + [CSR_SIE] =3D { "sie", smode, NULL, NULL, rmw_sie = }, + [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, - write_scounteren = }, + write_scounteren = }, =20 /* Supervisor Trap Handling */ [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 1f7aed23c9..75ee1c4971 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -282,8 +282,8 @@ static target_ulong type2_mcontrol_validate(CPURISCVSta= te *env, /* validate size encoding */ size =3D type2_breakpoint_size(env, ctrl); if (access_size[size] =3D=3D -1) { - qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using S= IZE_ANY\n", - size); + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " + "SIZE_ANY\n", size); } else { val |=3D (ctrl & TYPE2_SIZELO); if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { @@ -411,8 +411,8 @@ static target_ulong type6_mcontrol6_validate(CPURISCVSt= ate *env, /* validate size encoding */ size =3D extract32(ctrl, 16, 4); if (access_size[size] =3D=3D -1) { - qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using S= IZE_ANY\n", - size); + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using " + "SIZE_ANY\n", size); } else { val |=3D (ctrl & TYPE6_SIZE); } @@ -696,7 +696,8 @@ target_ulong tdata_csr_read(CPURISCVState *env, int tda= ta_index) int trigger_type; switch (tdata_index) { case TDATA1: - trigger_type =3D extract_trigger_type(env, env->tdata1[env->trigge= r_cur]); + trigger_type =3D extract_trigger_type(env, + env->tdata1[env->trigger_cur]); if ((trigger_type =3D=3D TRIGGER_TYPE_INST_CNT) && icount_enabled(= )) { return deposit64(env->tdata1[env->trigger_cur], 10, 14, itrigger_get_adjust_count(env)); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 692bbb64f6..fa537aed74 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -321,7 +321,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) } if (env->misa_ext & RVV) { int base_reg =3D cs->gdb_num_regs; - gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_v= ector, + gdb_register_coprocessor(cs, riscv_gdb_get_vector, + riscv_gdb_set_vector, ricsv_gen_dynamic_vector_xml(cs, base_reg= ), "riscv-vector.xml", 0); } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 6ab2ae81c7..1f5aca42e8 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -129,7 +129,8 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t = pmp_index, uint8_t val) } } =20 -static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulon= g *ea) +static void pmp_decode_napot(target_ulong a, target_ulong *sa, + target_ulong *ea) { /* * aaaa...aaa0 8-byte NAPOT range @@ -217,7 +218,8 @@ static void pmp_update_rule(CPURISCVState *env, uint32_= t pmp_index) pmp_update_rule_nums(env); } =20 -static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong= addr) +static int pmp_is_in_range(CPURISCVState *env, int pmp_index, + target_ulong addr) { int result =3D 0; =20 diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 48ad60be2b..db06b3882f 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -419,7 +419,8 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t = value, uint32_t ctr_idx) } else { return -1; } - overflow_at =3D (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + over= flow_ns; + overflow_at =3D (uint64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_ns; =20 if (overflow_at > INT64_MAX) { overflow_left +=3D overflow_at - INT64_MAX; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 81ac85b7d5..f4d0438988 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -382,8 +382,8 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState= *env, uint32_t desc, } =20 /* - * masked unit-stride load and store operation will be a special case of s= tride, - * stride =3D NF * sizeof (MTYPE) + * masked unit-stride load and store operation will be a special case of + * stride, stride =3D NF * sizeof (MTYPE) */ =20 #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ @@ -678,7 +678,8 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, /* load/store rest of elements of current segment pointed by vstar= t */ for (pos =3D off; pos < max_elems; pos++, env->vstart++) { target_ulong addr =3D base + ((pos + k * max_elems) << log2_es= z); - ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd= , ra); + ldst_elem(env, adjust_addr(env, addr), pos + k * max_elems, vd, + ra); } k++; } @@ -1306,7 +1307,9 @@ GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H= 2, DO_SRL, 0xf) GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f) GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f) =20 -/* generate the helpers for shift instructions with one vector and one sca= lar */ +/* + * generate the helpers for shift instructions with one vector and one sca= lar + */ #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, \ @@ -2165,7 +2168,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ do_##NAME, ESZ); \ } =20 -static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint= 8_t b) +static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, + uint8_t b) { uint8_t res =3D a + b; if (res < a) { @@ -2309,7 +2313,8 @@ static inline int8_t sadd8(CPURISCVState *env, int vx= rm, int8_t a, int8_t b) return res; } =20 -static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int1= 6_t b) +static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, + int16_t b) { int16_t res =3D a + b; if ((res ^ a) & (res ^ b) & INT16_MIN) { @@ -2319,7 +2324,8 @@ static inline int16_t sadd16(CPURISCVState *env, int = vxrm, int16_t a, int16_t b) return res; } =20 -static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int32_t res =3D a + b; if ((res ^ a) & (res ^ b) & INT32_MIN) { @@ -2329,7 +2335,8 @@ static inline int32_t sadd32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return res; } =20 -static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D a + b; if ((res ^ a) & (res ^ b) & INT64_MIN) { @@ -2357,7 +2364,8 @@ GEN_VEXT_VX_RM(vsadd_vx_h, 2) GEN_VEXT_VX_RM(vsadd_vx_w, 4) GEN_VEXT_VX_RM(vsadd_vx_d, 8) =20 -static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint= 8_t b) +static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, + uint8_t b) { uint8_t res =3D a - b; if (res > a) { @@ -2428,7 +2436,8 @@ static inline int8_t ssub8(CPURISCVState *env, int vx= rm, int8_t a, int8_t b) return res; } =20 -static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int1= 6_t b) +static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, + int16_t b) { int16_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT16_MIN) { @@ -2438,7 +2447,8 @@ static inline int16_t ssub16(CPURISCVState *env, int = vxrm, int16_t a, int16_t b) return res; } =20 -static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int32_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT32_MIN) { @@ -2448,7 +2458,8 @@ static inline int32_t ssub32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return res; } =20 -static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D a - b; if ((res ^ a) & (a ^ b) & INT64_MIN) { @@ -2504,7 +2515,8 @@ static inline uint8_t get_round(int vxrm, uint64_t v,= uint8_t shift) return 0; /* round-down (truncate) */ } =20 -static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int64_t res =3D (int64_t)a + b; uint8_t round =3D get_round(vxrm, res, 1); @@ -2512,7 +2524,8 @@ static inline int32_t aadd32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return (res >> 1) + round; } =20 -static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D a + b; uint8_t round =3D get_round(vxrm, res, 1); @@ -2577,7 +2590,8 @@ GEN_VEXT_VX_RM(vaaddu_vx_h, 2) GEN_VEXT_VX_RM(vaaddu_vx_w, 4) GEN_VEXT_VX_RM(vaaddu_vx_d, 8) =20 -static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int3= 2_t b) +static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, + int32_t b) { int64_t res =3D (int64_t)a - b; uint8_t round =3D get_round(vxrm, res, 1); @@ -2585,7 +2599,8 @@ static inline int32_t asub32(CPURISCVState *env, int = vxrm, int32_t a, int32_t b) return (res >> 1) + round; } =20 -static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int6= 4_t b) +static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, + int64_t b) { int64_t res =3D (int64_t)a - b; uint8_t round =3D get_round(vxrm, res, 1); @@ -4498,7 +4513,9 @@ RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, flo= at32_to_int64) GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 4) GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8) =20 -/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width fl= oat */ +/* + * vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width fl= oat. + */ RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16) RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) @@ -4515,8 +4532,7 @@ GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4) GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8) =20 /* - * vfwcvt.f.f.v vd, vs2, vm - * Convert single-width float to double-width float. + * vfwcvt.f.f.v vd, vs2, vm # Convert single-width float to double-width f= loat. */ static uint32_t vfwcvtffv16(uint16_t a, float_status *s) { @@ -4549,7 +4565,9 @@ GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1) GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2) GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4) =20 -/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to fl= oat */ +/* + * vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to fl= oat. + */ RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16) RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32) GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2) @@ -4699,14 +4717,20 @@ GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H= 4, H4, float32_add) GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) =20 /* Maximum value */ -GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_n= umber) -GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maximum_n= umber) -GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maximum_n= umber) +GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, + float16_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, + float32_maximum_number) +GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, + float64_maximum_number) =20 /* Minimum value */ -GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minimum_n= umber) -GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minimum_n= umber) -GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minimum_n= umber) +GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, + float16_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, + float32_minimum_number) +GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, + float64_minimum_number) =20 /* Vector Widening Floating-Point Add Instructions */ static uint32_t fwadd16(uint32_t a, uint16_t b, float_status *s) --=20 2.25.1