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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680111118692100011 Content-Type: text/plain; charset="utf-8" Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 7 +++---- target/riscv/cpu.h | 1 - 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 63efd1b313..693ff10cab 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -400,7 +400,6 @@ static void rv64_thead_c906_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_11_0); =20 cpu->cfg.ext_g =3D true; - cpu->cfg.ext_c =3D true; cpu->cfg.ext_u =3D true; cpu->cfg.ext_s =3D true; cpu->cfg.ext_icsr =3D true; @@ -1108,7 +1107,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_d) { ext |=3D RVD; } - if (riscv_cpu_cfg(env)->ext_c) { + if (riscv_has_ext(env, RVC)) { ext |=3D RVC; } if (riscv_cpu_cfg(env)->ext_s) { @@ -1438,6 +1437,8 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor= *v, const char *name, static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { {.name =3D "a", .description =3D "Atomic instructions", .misa_bit =3D RVA, .enabled =3D true}, + {.name =3D "c", .description =3D "Compressed instructions", + .misa_bit =3D RVC, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1466,7 +1467,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), - DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1580,7 +1580,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_c =3D misa_ext & RVC; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; cpu->cfg.ext_h =3D misa_ext & RVH; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f703888310..c6dc24d236 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -424,7 +424,6 @@ struct RISCVCPUConfig { bool ext_m; bool ext_f; bool ext_d; - bool ext_c; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2