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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680111034033100001 Content-Type: text/plain; charset="utf-8" Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 16 ++++++++-------- target/riscv/cpu.h | 1 - 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d7763ecfa9..63efd1b313 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -812,13 +812,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && + riscv_has_ext(env, RVA) && + cpu->cfg.ext_f && cpu->cfg.ext_d && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; cpu->cfg.ext_f =3D true; cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; @@ -862,7 +861,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) return; } =20 - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1100,7 +1099,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_cpu_cfg(env)->ext_m) { ext |=3D RVM; } - if (riscv_cpu_cfg(env)->ext_a) { + if (riscv_has_ext(env, RVA)) { ext |=3D RVA; } if (riscv_cpu_cfg(env)->ext_f) { @@ -1436,7 +1435,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visito= r *v, const char *name, visit_type_bool(v, name, &value, errp); } =20 -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D {}; +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + {.name =3D "a", .description =3D "Atomic instructions", + .misa_bit =3D RVA, .enabled =3D true}, +}; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) { @@ -1462,7 +1464,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), - DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), @@ -1576,7 +1577,6 @@ static void register_cpu_props(Object *obj) cpu->cfg.ext_i =3D misa_ext & RVI; cpu->cfg.ext_e =3D misa_ext & RVE; cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_a =3D misa_ext & RVA; cpu->cfg.ext_f =3D misa_ext & RVF; cpu->cfg.ext_d =3D misa_ext & RVD; cpu->cfg.ext_v =3D misa_ext & RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..f703888310 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -422,7 +422,6 @@ struct RISCVCPUConfig { bool ext_e; bool ext_g; bool ext_m; - bool ext_a; bool ext_f; bool ext_d; bool ext_c; --=20 2.39.2