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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680110983978100001 Content-Type: text/plain; charset="utf-8" When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The current solution is to sync everything at the end of validate_set_extensions(), checking every cpu->cfg.ext_N value to do a set_misa() in the end. The last change we're making in the MISA cfg flags are in the G extension logic, enabling IMAFG if cpu->cfg_ext.g is enabled. Otherwise we're not making any changes in MISA bits ever since realize() starts. There's no reason to postpone misa_ext updates until the end of the validation. Let's do it earlier, during realize(), in a new helper called riscv_cpu_sync_misa_cfg(). If cpu->cfg.ext_g is enabled, do it again by updating env->misa_ext* directly. This is a pre-requisite to allow riscv_cpu_validate_set_extensions() to use riscv_has_ext() instead of cpu->cfg.ext_N to validate the MISA extensions, which is our end goal here. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 94 +++++++++++++++++++++++++++------------------- 1 file changed, 56 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..2711d80e16 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -804,12 +804,11 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) =20 /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, doing a set_misa() in the end. + * cpu->cfg accordingly. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; - uint32_t ext =3D 0; =20 /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && @@ -824,6 +823,9 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_d =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; + + env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; + env->misa_ext_mask =3D env->misa_ext; } =20 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { @@ -962,39 +964,8 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU= *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } if (cpu->cfg.ext_v) { int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, "Vector extension VLEN must be power of 2"); @@ -1032,11 +1003,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) } set_vext_version(env, vext_version); } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } - - set_misa(env, env->misa_mxl, ext); } =20 #ifndef CONFIG_USER_ONLY @@ -1121,6 +1087,50 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 +static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) +{ + uint32_t ext =3D 0; + + if (riscv_cpu_cfg(env)->ext_i) { + ext |=3D RVI; + } + if (riscv_cpu_cfg(env)->ext_e) { + ext |=3D RVE; + } + if (riscv_cpu_cfg(env)->ext_m) { + ext |=3D RVM; + } + if (riscv_cpu_cfg(env)->ext_a) { + ext |=3D RVA; + } + if (riscv_cpu_cfg(env)->ext_f) { + ext |=3D RVF; + } + if (riscv_cpu_cfg(env)->ext_d) { + ext |=3D RVD; + } + if (riscv_cpu_cfg(env)->ext_c) { + ext |=3D RVC; + } + if (riscv_cpu_cfg(env)->ext_s) { + ext |=3D RVS; + } + if (riscv_cpu_cfg(env)->ext_u) { + ext |=3D RVU; + } + if (riscv_cpu_cfg(env)->ext_h) { + ext |=3D RVH; + } + if (riscv_cpu_cfg(env)->ext_v) { + ext |=3D RVV; + } + if (riscv_cpu_cfg(env)->ext_j) { + ext |=3D RVJ; + } + + env->misa_ext =3D env->misa_ext_mask =3D ext; +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1156,6 +1166,14 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 + /* + * We can't be sure of whether we set defaults during cpu_init() + * or whether the user enabled/disabled some bits via cpu->cfg + * flags. Sync env->misa_ext with cpu->cfg now to allow us to + * use just env->misa_ext later. + */ + riscv_cpu_sync_misa_cfg(env); + /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && --=20 2.39.2