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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680111068260100003 Content-Type: text/plain; charset="utf-8" This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu->cfg.ext_N left that has an existing MISA bit (cfg.ext_g will be handled shortly). The function is now a no-op, simply copying the existing values of misa_ext* back to misa_ext*. Remove it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 52 ---------------------------------------------- 1 file changed, 52 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b40a55bc8d..3eb3b7dc59 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1081,50 +1081,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 -static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) -{ - uint32_t ext =3D 0; - - if (riscv_has_ext(env, RVI)) { - ext |=3D RVI; - } - if (riscv_has_ext(env, RVE)) { - ext |=3D RVE; - } - if (riscv_has_ext(env, RVM)) { - ext |=3D RVM; - } - if (riscv_has_ext(env, RVA)) { - ext |=3D RVA; - } - if (riscv_has_ext(env, RVF)) { - ext |=3D RVF; - } - if (riscv_has_ext(env, RVD)) { - ext |=3D RVD; - } - if (riscv_has_ext(env, RVC)) { - ext |=3D RVC; - } - if (riscv_has_ext(env, RVS)) { - ext |=3D RVS; - } - if (riscv_has_ext(env, RVU)) { - ext |=3D RVU; - } - if (riscv_has_ext(env, RVH)) { - ext |=3D RVH; - } - if (riscv_has_ext(env, RVV)) { - ext |=3D RVV; - } - if (riscv_has_ext(env, RVJ)) { - ext |=3D RVJ; - } - - env->misa_ext =3D env->misa_ext_mask =3D ext; -} - static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -1168,14 +1124,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) set_priv_version(env, priv_version); } =20 - /* - * We can't be sure of whether we set defaults during cpu_init() - * or whether the user enabled/disabled some bits via cpu->cfg - * flags. Sync env->misa_ext with cpu->cfg now to allow us to - * use just env->misa_ext later. - */ - riscv_cpu_sync_misa_cfg(env); - riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.39.2