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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1680111166956100004 Content-Type: text/plain; charset="utf-8" Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 12 +++++------- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 86edc08545..b40a55bc8d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -876,7 +876,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) } =20 /* The V vector extension depends on the Zve64d extension */ - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { cpu->cfg.ext_zve64d =3D true; } =20 @@ -958,7 +958,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU = *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_v) { + if (riscv_has_ext(env, RVV)) { int vext_version =3D VEXT_VERSION_1_00_0; if (!is_power_of_2(cpu->cfg.vlen)) { error_setg(errp, @@ -1115,7 +1115,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVH)) { ext |=3D RVH; } - if (riscv_cpu_cfg(env)->ext_v) { + if (riscv_has_ext(env, RVV)) { ext |=3D RVV; } if (riscv_has_ext(env, RVJ)) { @@ -1453,6 +1453,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVH, .enabled =3D true}, {.name =3D "x-j", .description =3D "Dynamic translated languages", .misa_bit =3D RVJ, .enabled =3D false}, + {.name =3D "v", .description =3D "Vector operations", + .misa_bit =3D RVV, .enabled =3D false}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1476,7 +1478,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), @@ -1569,7 +1570,6 @@ static Property riscv_cpu_extensions[] =3D { static void register_cpu_props(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; DeviceState *dev =3D DEVICE(obj); =20 @@ -1579,8 +1579,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_v =3D misa_ext & RVV; - /* * We don't want to set the default riscv_cpu_extensions * in this case. diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 43a40ba950..c0280ace2a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_v; bool ext_zba; bool ext_zbb; bool ext_zbc; --=20 2.39.2