From nobody Sat Feb 7 05:37:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1679972861349552.5626472048629; Mon, 27 Mar 2023 20:07:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgzgB-0007Sw-9y; Mon, 27 Mar 2023 23:07:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgzg3-0007Lv-5u for qemu-devel@nongnu.org; Mon, 27 Mar 2023 23:07:15 -0400 Received: from mail.loongson.cn ([114.242.206.163] helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgzg0-0000ta-Ep for qemu-devel@nongnu.org; Mon, 27 Mar 2023 23:07:14 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxJMTUWSJkpNoSAA--.17546S3; Tue, 28 Mar 2023 11:07:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dxyr24WSJkZukOAA--.10252S46; Tue, 28 Mar 2023 11:06:59 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [RFC PATCH v2 44/44] target/loongarch: Use {set/get}_gpr replace to cpu_fpr Date: Tue, 28 Mar 2023 11:06:31 +0800 Message-Id: <20230328030631.3117129-45-gaosong@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230328030631.3117129-1-gaosong@loongson.cn> References: <20230328030631.3117129-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Dxyr24WSJkZukOAA--.10252S46 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjvAXoWfJF17uF4xAF4DAr1Dtr18Xwb_yoW8XrykZo Z7X3WUArZ7Jr43uF9akFs7XFW2vFy7Wa1fAws09a4kWa1xur18t3WrGwn8ZayUGF9Fgryf W3Z3tF9rJ34xAr1Dn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnRJU UUqG1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l8cAvFVAK0II2c7xJM28CjxkF64 kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY 1x0267AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aV CY1x0267AKxVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x2 6I8E6xACxx1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x8ErcxFaVAv8VWrMcvjeVCFs4 IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCF04k20xvE74AG Y7Cv6cx26rWl4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s 026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1Y6r17MIIYrxkI7VAKI48JMIIF 0xvE2Ix0cI8IcVAFwI0_tr0E3s1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42 IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Cr0_Gr1UMIIF0xvEx4A2 jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0zRVWlkUUUUU= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1679972861673100001 Content-Type: text/plain; charset="utf-8" Introduce set_fpr() and get_fpr() and remove cpu_fpr. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- .../loongarch/insn_trans/trans_farith.c.inc | 72 +++++++++++++++---- target/loongarch/insn_trans/trans_fcmp.c.inc | 12 ++-- .../loongarch/insn_trans/trans_fmemory.c.inc | 37 ++++++---- target/loongarch/insn_trans/trans_fmov.c.inc | 31 +++++--- target/loongarch/translate.c | 20 ++++-- 5 files changed, 129 insertions(+), 43 deletions(-) diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loonga= rch/insn_trans/trans_farith.c.inc index 7081fbb89b..21ea47308b 100644 --- a/target/loongarch/insn_trans/trans_farith.c.inc +++ b/target/loongarch/insn_trans/trans_farith.c.inc @@ -17,18 +17,29 @@ static bool gen_fff(DisasContext *ctx, arg_fff *a, void (*func)(TCGv, TCGv_env, TCGv, TCGv)) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src1 =3D get_fpr(ctx, a->fj); + TCGv src2 =3D get_fpr(ctx, a->fk); + CHECK_FPE; =20 - func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]); + func(dest, cpu_env, src1, src2); + set_fpr(a->fd, dest); + return true; } =20 static bool gen_ff(DisasContext *ctx, arg_ff *a, void (*func)(TCGv, TCGv_env, TCGv)) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src =3D get_fpr(ctx, a->fj); + CHECK_FPE; =20 - func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]); + func(dest, cpu_env, src); + set_fpr(a->fd, dest); + return true; } =20 @@ -37,61 +48,98 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a, int flag) { TCGv_i32 tflag =3D tcg_constant_i32(flag); + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src1 =3D get_fpr(ctx, a->fj); + TCGv src2 =3D get_fpr(ctx, a->fk); + TCGv src3 =3D get_fpr(ctx, a->fa); =20 CHECK_FPE; =20 - func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], - cpu_fpr[a->fk], cpu_fpr[a->fa], tflag); + func(dest, cpu_env, src1, src2, src3, tflag); + set_fpr(a->fd, dest); + return true; } =20 static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src1 =3D get_fpr(ctx, a->fk); + TCGv src2 =3D get_fpr(ctx, a->fj); + CHECK_FPE; =20 - tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0,= 31); + tcg_gen_deposit_i64(dest, src1, src2, 0, 31); + set_fpr(a->fd, dest); + return true; } =20 static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src1 =3D get_fpr(ctx, a->fk); + TCGv src2 =3D get_fpr(ctx, a->fj); + CHECK_FPE; =20 - tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0,= 63); + tcg_gen_deposit_i64(dest, src1, src2, 0, 63); + set_fpr(a->fd, dest); + return true; } =20 static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src =3D get_fpr(ctx, a->fj); + CHECK_FPE; =20 - tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31= )); - gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]); + tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31)); + gen_nanbox_s(dest, dest); + set_fpr(a->fd, dest); + return true; } =20 static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src =3D get_fpr(ctx, a->fj); + CHECK_FPE; =20 - tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63= )); + tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63)); + set_fpr(a->fd, dest); + return true; } =20 static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src =3D get_fpr(ctx, a->fj); + CHECK_FPE; =20 - tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000); - gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]); + tcg_gen_xori_i64(dest, src, 0x80000000); + gen_nanbox_s(dest, dest); + set_fpr(a->fd, dest); + return true; } =20 static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a) { + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src =3D get_fpr(ctx, a->fj); + CHECK_FPE; =20 - tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL); + tcg_gen_xori_i64(dest, src, 0x8000000000000000LL); + set_fpr(a->fd, dest); + return true; } =20 diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarc= h/insn_trans/trans_fcmp.c.inc index 3b0da2b9f4..a78868dbc4 100644 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc @@ -25,17 +25,19 @@ static uint32_t get_fcmp_flags(int cond) =20 static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a) { - TCGv var; + TCGv var, src1, src2; uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); =20 CHECK_FPE; =20 var =3D tcg_temp_new(); + src1 =3D get_fpr(ctx, a->fj); + src2 =3D get_fpr(ctx, a->fk); fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s); flags =3D get_fcmp_flags(a->fcond >> 1); =20 - fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag= s)); + fn(var, cpu_env, src1, src2, tcg_constant_i32(flags)); =20 tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); return true; @@ -43,17 +45,19 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fc= mp_cond_s *a) =20 static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a) { - TCGv var; + TCGv var, src1, src2; uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); =20 CHECK_FPE; =20 var =3D tcg_temp_new(); + src1 =3D get_fpr(ctx, a->fj); + src2 =3D get_fpr(ctx, a->fk); fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d); flags =3D get_fcmp_flags(a->fcond >> 1); =20 - fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag= s)); + fn(var, cpu_env, src1, src2, tcg_constant_i32(flags)); =20 tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); return true; diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loong= arch/insn_trans/trans_fmemory.c.inc index 0d11843873..91c09fb6d9 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -13,6 +13,7 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop) static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) { TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); + TCGv dest =3D get_fpr(ctx, a->fd); =20 CHECK_FPE; =20 @@ -22,8 +23,9 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, M= emOp mop) addr =3D temp; } =20 - tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - maybe_nanbox_load(cpu_fpr[a->fd], mop); + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); + maybe_nanbox_load(dest, mop); + set_fpr(a->fd, dest); =20 return true; } @@ -31,6 +33,7 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, M= emOp mop) static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) { TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE); + TCGv src =3D get_fpr(ctx, a->fd); =20 CHECK_FPE; =20 @@ -40,7 +43,8 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, = MemOp mop) addr =3D temp; } =20 - tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); + tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop); + return true; } =20 @@ -48,14 +52,16 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, M= emOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); + TCGv dest =3D get_fpr(ctx, a->fd); TCGv addr; =20 CHECK_FPE; =20 addr =3D tcg_temp_new(); tcg_gen_add_tl(addr, src1, src2); - tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - maybe_nanbox_load(cpu_fpr[a->fd], mop); + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); + maybe_nanbox_load(dest, mop); + set_fpr(a->fd, dest); =20 return true; } @@ -64,13 +70,14 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, = MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); + TCGv src3 =3D get_fpr(ctx, a->fd); TCGv addr; =20 CHECK_FPE; =20 addr =3D tcg_temp_new(); tcg_gen_add_tl(addr, src1, src2); - tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); + tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 return true; } @@ -79,6 +86,7 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, M= emOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); + TCGv dest =3D get_fpr(ctx, a->fd); TCGv addr; =20 CHECK_FPE; @@ -86,8 +94,9 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, M= emOp mop) addr =3D tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); - tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - maybe_nanbox_load(cpu_fpr[a->fd], mop); + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); + maybe_nanbox_load(dest, mop); + set_fpr(a->fd, dest); =20 return true; } @@ -96,6 +105,7 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a,= MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); + TCGv src3 =3D get_fpr(ctx, a->fd); TCGv addr; =20 CHECK_FPE; @@ -103,7 +113,7 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a= , MemOp mop) addr =3D tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); - tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); + tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 return true; } @@ -112,6 +122,7 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a,= MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); + TCGv dest =3D get_fpr(ctx, a->fd); TCGv addr; =20 CHECK_FPE; @@ -119,8 +130,9 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a,= MemOp mop) addr =3D tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); - tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); - maybe_nanbox_load(cpu_fpr[a->fd], mop); + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); + maybe_nanbox_load(dest, mop); + set_fpr(a->fd, dest); =20 return true; } @@ -129,6 +141,7 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a= , MemOp mop) { TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); + TCGv src3 =3D get_fpr(ctx, a->fd); TCGv addr; =20 CHECK_FPE; @@ -136,7 +149,7 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a= , MemOp mop) addr =3D tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); tcg_gen_add_tl(addr, src1, src2); - tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop); + tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 return true; } diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarc= h/insn_trans/trans_fmov.c.inc index 069c941665..5af0dd1b66 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -10,14 +10,17 @@ static const uint32_t fcsr_mask[4] =3D { static bool trans_fsel(DisasContext *ctx, arg_fsel *a) { TCGv zero =3D tcg_constant_tl(0); + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src1 =3D get_fpr(ctx, a->fj); + TCGv src2 =3D get_fpr(ctx, a->fk); TCGv cond; =20 CHECK_FPE; =20 cond =3D tcg_temp_new(); tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); - tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero, - cpu_fpr[a->fj], cpu_fpr[a->fk]); + tcg_gen_movcond_tl(TCG_COND_EQ, dest, cond, zero, src1, src2); + set_fpr(a->fd, dest); =20 return true; } @@ -25,15 +28,16 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a) static bool gen_f2f(DisasContext *ctx, arg_ff *a, void (*func)(TCGv, TCGv), bool nanbox) { - TCGv dest =3D cpu_fpr[a->fd]; - TCGv src =3D cpu_fpr[a->fj]; + TCGv dest =3D get_fpr(ctx, a->fd); + TCGv src =3D get_fpr(ctx, a->fj); =20 CHECK_FPE; =20 func(dest, src); if (nanbox) { - gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]); + gen_nanbox_s(dest, dest); } + set_fpr(a->fd, dest); =20 return true; } @@ -42,10 +46,13 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a, void (*func)(TCGv, TCGv)) { TCGv src =3D gpr_src(ctx, a->rj, EXT_NONE); + TCGv dest =3D get_fpr(ctx, a->fd); =20 CHECK_FPE; =20 - func(cpu_fpr[a->fd], src); + func(dest, src); + set_fpr(a->fd, dest); + return true; } =20 @@ -53,10 +60,11 @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a, void (*func)(TCGv, TCGv)) { TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); + TCGv src =3D get_fpr(ctx, a->fj); =20 CHECK_FPE; =20 - func(dest, cpu_fpr[a->fj]); + func(dest, src); gen_set_gpr(a->rd, dest, EXT_NONE); =20 return true; @@ -124,11 +132,12 @@ static void gen_movfrh2gr_s(TCGv dest, TCGv src) static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a) { TCGv t0; + TCGv src =3D get_fpr(ctx, a->fj); =20 CHECK_FPE; =20 t0 =3D tcg_temp_new(); - tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1); + tcg_gen_andi_tl(t0, src, 0x1); tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); =20 return true; @@ -136,10 +145,14 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_mov= fr2cf *a) =20 static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a) { + TCGv dest =3D get_fpr(ctx, a->fd); + CHECK_FPE; =20 - tcg_gen_ld8u_tl(cpu_fpr[a->fd], cpu_env, + tcg_gen_ld8u_tl(dest, cpu_env, offsetof(CPULoongArchState, cf[a->cj & 0x7])); + set_fpr(a->fd, dest); + return true; } =20 diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 7f2ad7f542..dbf8545c9d 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -23,7 +23,6 @@ /* Global register indices */ TCGv cpu_gpr[32], cpu_pc; static TCGv cpu_lladdr, cpu_llval; -TCGv_i64 cpu_fpr[32]; =20 #include "exec/gen-icount.h" =20 @@ -174,6 +173,20 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExte= nd dst_ext) } } =20 +static TCGv get_fpr(DisasContext *ctx, int reg_num) +{ + TCGv t =3D tcg_temp_new(); + tcg_gen_ld_i64(t, cpu_env, + offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); + return t; +} + +static void set_fpr(int reg_num, TCGv val) +{ + tcg_gen_st_i64(val, cpu_env, + offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); +} + #include "decode-insns.c.inc" #include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_shift.c.inc" @@ -268,11 +281,6 @@ void loongarch_translate_init(void) regnames[i]); } =20 - for (i =3D 0; i < 32; i++) { - int off =3D offsetof(CPULoongArchState, fpr[i]); - cpu_fpr[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); - } - cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc)= , "pc"); cpu_lladdr =3D tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, lladdr), "lladdr"); --=20 2.31.1