From nobody Sat Feb 7 05:36:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167997313945597.12656761665164; Mon, 27 Mar 2023 20:12:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgzg2-0007LR-DQ; Mon, 27 Mar 2023 23:07:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pgzfn-0007Fz-RM for qemu-devel@nongnu.org; Mon, 27 Mar 2023 23:06:59 -0400 Received: from mail.loongson.cn ([114.242.206.163] helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pgzfl-0000ZO-L4 for qemu-devel@nongnu.org; Mon, 27 Mar 2023 23:06:59 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxJPzFWSJkdtoSAA--.28806S3; Tue, 28 Mar 2023 11:06:45 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dxyr24WSJkZukOAA--.10252S26; Tue, 28 Mar 2023 11:06:44 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [RFC PATCH v2 24/44] target/loongarch: Implement vsllwil vextl Date: Tue, 28 Mar 2023 11:06:11 +0800 Message-Id: <20230328030631.3117129-25-gaosong@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230328030631.3117129-1-gaosong@loongson.cn> References: <20230328030631.3117129-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Dxyr24WSJkZukOAA--.10252S26 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjvJXoW3XFWxXrW7Ar1DZrWUXrW8JFb_yoW7tw4UpF 47Kry7Gr48JrWxX3Zava4rAF1DZr4DKw1j9w4fta48WrW7JF1DtF1vq39FkF45W3ZxXrW0 v3W7A3yY9FW5X37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bnkFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4 AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF 7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6x kF7I0E14v26r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020E x4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E74AGY7Cv6cx26rWlOx8S6xCaFV Cjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7VAKI48JMxAIw28IcVCjz48v 1sIEY20_WwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I 0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAI cVC0I7IYx2IY67AKxVW7JVWDJwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcV CF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIE c7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0zRVWlkUUUUU= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1679973141387100003 Content-Type: text/plain; charset="utf-8" This patch includes: - VSLLWIL.{H.B/W.H/D.W}; - VSLLWIL.{HU.BU/WU.HU/DU.WU}; - VEXTL.Q.D, VEXTL.QU.DU. Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/disas.c | 9 +++++ target/loongarch/helper.h | 9 +++++ target/loongarch/insn_trans/trans_lsx.c.inc | 21 +++++++++++ target/loongarch/insns.decode | 9 +++++ target/loongarch/lsx_helper.c | 40 +++++++++++++++++++++ 5 files changed, 88 insertions(+) diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index f7d0fb4441..087cac10ad 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1139,3 +1139,12 @@ INSN_LSX(vrotri_b, vv_i) INSN_LSX(vrotri_h, vv_i) INSN_LSX(vrotri_w, vv_i) INSN_LSX(vrotri_d, vv_i) + +INSN_LSX(vsllwil_h_b, vv_i) +INSN_LSX(vsllwil_w_h, vv_i) +INSN_LSX(vsllwil_d_w, vv_i) +INSN_LSX(vextl_q_d, vv) +INSN_LSX(vsllwil_hu_bu, vv_i) +INSN_LSX(vsllwil_wu_hu, vv_i) +INSN_LSX(vsllwil_du_wu, vv_i) +INSN_LSX(vextl_qu_du, vv) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index 1eeb614427..0266b9a4ad 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -367,3 +367,12 @@ DEF_HELPER_3(vmskgez_b, void, env, i32, i32) DEF_HELPER_3(vmsknz_b, void, env, i32,i32) =20 DEF_HELPER_FLAGS_4(vnori_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) + +DEF_HELPER_4(vsllwil_h_b, void, env, i32, i32, i32) +DEF_HELPER_4(vsllwil_w_h, void, env, i32, i32, i32) +DEF_HELPER_4(vsllwil_d_w, void, env, i32, i32, i32) +DEF_HELPER_3(vextl_q_d, void, env, i32, i32) +DEF_HELPER_4(vsllwil_hu_bu, void, env, i32, i32, i32) +DEF_HELPER_4(vsllwil_wu_hu, void, env, i32, i32, i32) +DEF_HELPER_4(vsllwil_du_wu, void, env, i32, i32, i32) +DEF_HELPER_3(vextl_qu_du, void, env, i32, i32) diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch= /insn_trans/trans_lsx.c.inc index 84c8d92ad6..fb40aaf5ad 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -39,6 +39,18 @@ static bool gen_vv(DisasContext *ctx, arg_vv *a, return true; } =20 +static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a, + void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 vd =3D tcg_constant_i32(a->vd); + TCGv_i32 vj =3D tcg_constant_i32(a->vj); + TCGv_i32 imm =3D tcg_constant_i32(a->imm); + + CHECK_SXE; + func(cpu_env, vd, vj, imm); + return true; +} + static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop, void (*func)(unsigned, uint32_t, uint32_t, uint32_t, uint32_t, uint32_t)) @@ -2654,3 +2666,12 @@ TRANS(vrotri_b, gvec_vv_i, MO_8, tcg_gen_gvec_rotri) TRANS(vrotri_h, gvec_vv_i, MO_16, tcg_gen_gvec_rotri) TRANS(vrotri_w, gvec_vv_i, MO_32, tcg_gen_gvec_rotri) TRANS(vrotri_d, gvec_vv_i, MO_64, tcg_gen_gvec_rotri) + +TRANS(vsllwil_h_b, gen_vv_i, gen_helper_vsllwil_h_b) +TRANS(vsllwil_w_h, gen_vv_i, gen_helper_vsllwil_w_h) +TRANS(vsllwil_d_w, gen_vv_i, gen_helper_vsllwil_d_w) +TRANS(vextl_q_d, gen_vv, gen_helper_vextl_q_d) +TRANS(vsllwil_hu_bu, gen_vv_i, gen_helper_vsllwil_hu_bu) +TRANS(vsllwil_wu_hu, gen_vv_i, gen_helper_vsllwil_wu_hu) +TRANS(vsllwil_du_wu, gen_vv_i, gen_helper_vsllwil_du_wu) +TRANS(vextl_qu_du, gen_vv, gen_helper_vextl_qu_du) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 7c0b0c4ac8..23dd338026 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -839,3 +839,12 @@ vrotri_b 0111 00101010 00000 01 ... ..... ....= . @vv_ui3 vrotri_h 0111 00101010 00000 1 .... ..... ..... @vv_ui4 vrotri_w 0111 00101010 00001 ..... ..... ..... @vv_ui5 vrotri_d 0111 00101010 0001 ...... ..... ..... @vv_ui6 + +vsllwil_h_b 0111 00110000 10000 01 ... ..... ..... @vv_ui3 +vsllwil_w_h 0111 00110000 10000 1 .... ..... ..... @vv_ui4 +vsllwil_d_w 0111 00110000 10001 ..... ..... ..... @vv_ui5 +vextl_q_d 0111 00110000 10010 00000 ..... ..... @vv +vsllwil_hu_bu 0111 00110000 11000 01 ... ..... ..... @vv_ui3 +vsllwil_wu_hu 0111 00110000 11000 1 .... ..... ..... @vv_ui4 +vsllwil_du_wu 0111 00110000 11001 ..... ..... ..... @vv_ui5 +vextl_qu_du 0111 00110000 11010 00000 ..... ..... @vv diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c index 198ab3088b..72efdd5a74 100644 --- a/target/loongarch/lsx_helper.c +++ b/target/loongarch/lsx_helper.c @@ -1031,3 +1031,43 @@ void HELPER(vnori_b)(void *vd, void *vj, uint64_t im= m, uint32_t v) Vd->B(i) =3D ~(Vj->B(i) | (uint8_t)imm); } } + +#define VSLLWIL(NAME, BIT, T1, T2, E1, E2) \ +void HELPER(NAME)(CPULoongArchState *env, \ + uint32_t vd, uint32_t vj, uint32_t imm) \ +{ \ + int i; \ + VReg temp; \ + VReg *Vd =3D &(env->fpr[vd].vreg); \ + VReg *Vj =3D &(env->fpr[vj].vreg); \ + temp.D(0) =3D 0; \ + temp.D(1) =3D 0; \ + for (i =3D 0; i < LSX_LEN/BIT; i++) { \ + temp.E1(i) =3D (T1)(T2)Vj->E2(i) << (imm % BIT); \ + } \ + Vd->D(0) =3D temp.D(0); \ + Vd->D(1) =3D temp.D(1); \ +} + +void HELPER(vextl_q_d)(CPULoongArchState *env, uint32_t vd, uint32_t vj) +{ + VReg *Vd =3D &(env->fpr[vd].vreg); + VReg *Vj =3D &(env->fpr[vj].vreg); + + Vd->Q(0) =3D int128_makes64(Vj->D(0)); +} + +void HELPER(vextl_qu_du)(CPULoongArchState *env, uint32_t vd, uint32_t vj) +{ + VReg *Vd =3D &(env->fpr[vd].vreg); + VReg *Vj =3D &(env->fpr[vj].vreg); + + Vd->Q(0) =3D int128_make64(Vj->D(0)); +} + +VSLLWIL(vsllwil_h_b, 16, int16_t, int8_t, H, B) +VSLLWIL(vsllwil_w_h, 32, int32_t, int16_t, W, H) +VSLLWIL(vsllwil_d_w, 64, int64_t, int32_t, D, W) +VSLLWIL(vsllwil_hu_bu, 16, uint16_t, uint8_t, H, B) +VSLLWIL(vsllwil_wu_hu, 32, uint32_t, uint16_t, W, H) +VSLLWIL(vsllwil_du_wu, 64, uint64_t, uint32_t, D, W) --=20 2.31.1