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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id s9-20020a4a9689000000b005255e556399sm11985361ooi.43.2023.03.27.15.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 15:50:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679957423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fFBbPXuZjV6eddXwXT4KhzyORLANTgVnsa8jR4GuZjI=; b=CRJQmhblQghvhqXwttXWaXFeek/1yz2WotbdPRpTvse4gD8HbgELdX59FaaUz7mLtd m0f64BMfxXqDsBQBEcYqPN3E2yaBUNIDRrAvyH94mrjbvm5z5JMdZJNwhVYodWvH1FrT t4Msvq8VrE/qHwi6AFCZj7XC9DanaEWU6GMDdDWWGFUxZjGzhKPIOAq3b35aMDE4VH8G 7xkHixzYPcocdi9NJioiUQADDCdXj24Srjb+EDTRuW+8o6fzAUwhGjNtXlWMWnl9mKRR C2BpAC5w2L/uqoJ0bycN7CAMfBlLV5V/faa2cG6utGDx1ncW3WsTW64IE15PjaAh45rq 2Jqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679957423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fFBbPXuZjV6eddXwXT4KhzyORLANTgVnsa8jR4GuZjI=; b=lRYb8nahmq02XU82molM2oAak6Y2RPQ41/NTzKAiS2HPs1TjIZmJQZ95Ul8DAZzaMZ 4pD0yisTJnm/xq6Uh+qNSA54qlt3gLvozYIqFNI2MtgkywTGeAGh3Nsmv7UFf6J0g+Gh gEwVUvMbTsEnLNvTJhwOrbvWHTdxd67odc2Li5H6Vn5pM4tqzoxQFGZFIj7hZJy1AGEo RMP2dwSSUNfrF2JupN0xGCMuzjYG7caYBPbMJ+P8CBdcHlz+nmB54R5/Ns0p8p9tC3cS Lp34pJVlIWwprtv5CUzUXYltRHiXqD6tXKTYuRBXttDo6YiM4EseVN6BddL39+wNdbPG YVvQ== X-Gm-Message-State: AO0yUKVT/YqkTZdZX/U2+7QIb6JtF35FOi9XgF+kX3INVanovupc2El1 gH/blA7932X7ER6wsvYQVtbDsIx5eQmmUd/WW9M= X-Google-Smtp-Source: AK7set8B9zTJkfRtm1B8QkCAi294oogDPjxB1gCVp9tEbu8oGtdCDankEvU71m7WafQL3fsrOo54zg== X-Received: by 2002:a05:6808:659:b0:384:4585:737f with SMTP id z25-20020a056808065900b003844585737fmr5874215oih.14.1679957423644; Mon, 27 Mar 2023 15:50:23 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 10/19] target/riscv: remove cpu->cfg.ext_m Date: Mon, 27 Mar 2023 19:49:25 -0300 Message-Id: <20230327224934.363314-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230327224934.363314-1-dbarboza@ventanamicro.com> References: <20230327224934.363314-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679957506390100001 Content-Type: text/plain; charset="utf-8" Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 10 +++++----- target/riscv/cpu.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b580eee9a..67a7d518c1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -811,13 +811,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) CPURISCVState *env =3D &cpu->env; =20 /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && + if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && + riscv_has_ext(env, RVM) && riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && riscv_has_ext(env, RVD) && cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_m =3D true; cpu->cfg.ext_icsr =3D true; cpu->cfg.ext_ifencei =3D true; =20 @@ -1094,7 +1094,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *en= v) if (riscv_has_ext(env, RVE)) { ext |=3D RVE; } - if (riscv_cpu_cfg(env)->ext_m) { + if (riscv_has_ext(env, RVM)) { ext |=3D RVM; } if (riscv_has_ext(env, RVA)) { @@ -1446,6 +1446,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = =3D { .misa_bit =3D RVI, .enabled =3D true}, {.name =3D "e", .description =3D "Base integer instruction set (embedd= ed)", .misa_bit =3D RVE, .enabled =3D false}, + {.name =3D "m", .description =3D "Integer multiplication and division", + .misa_bit =3D RVM, .enabled =3D true}, }; =20 static void riscv_cpu_add_misa_properties(Object *cpu_obj) @@ -1469,7 +1471,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu= _obj) static Property riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), - DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), @@ -1577,7 +1578,6 @@ static void register_cpu_props(Object *obj) * later on. */ if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_m =3D misa_ext & RVM; cpu->cfg.ext_v =3D misa_ext & RVV; cpu->cfg.ext_s =3D misa_ext & RVS; cpu->cfg.ext_u =3D misa_ext & RVU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cc0b9e73ac..7a42c80b7d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -419,7 +419,6 @@ typedef struct { =20 struct RISCVCPUConfig { bool ext_g; - bool ext_m; bool ext_s; bool ext_u; bool ext_h; --=20 2.39.2