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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id ax35-20020a05687c022300b0017243edbe5bsm5586817oac.58.2023.03.22.15.21.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 15:21:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1679523681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aw+7wAt+UOzc0KBymK9byKqs7rrsubq5pvYdEehGPjI=; b=kSt4H7Br7gGSn4NPk4eWUQ/HPjegEM768OULLMtMy2PO5uzN28K75hE98QQcw3N1aw 74LKaunUeXyFuTvklZeDVxfPlW/S88mwlKSnNx7e6IgzSGwqXmbN386tGZtz0abe3rXS GAU7Yjim4lmiFBq1kD0Dbag+WuxyL9X0nG2ria/nGjOZD1MsuuVcZ+ojhRPAyPynzUBJ dRnHv4xVIwWj9WUGM33U7IVEUpJESmxaV1Hwt1JC/D0EZ/1r17mqRukGzvcLDToU7axy FYS+MYdB0s0Frq2CZTrZjpBB28g87TgZ1iDOBI1Qd+JrVryz07LsoJztY6Y3MoWh55Go 9nrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679523681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aw+7wAt+UOzc0KBymK9byKqs7rrsubq5pvYdEehGPjI=; b=y+NXiPJoLWnMTTp9B9gMEwsGPI59KD0dpybJw2VGk6uVZhJVoKOwGMyus/mzeh++5M T8hx04mcAoTCR3Omg1TLaTSfvXsgEf5wFi3W+d99MjIKbcmEPCKmQjeYYwYCBJ3XlZtI MeqMY/Oxhlm47Uqa27fCTV/rvmef58ZHIRrdbgOx7zzAIaVxx4I4r+l6KfOOwtBh5Pjx JHZzHPcQHzCq4Ejy34OOriV53yjQUo8XjoGMmgT2EMfb9Dn/xUVnwTiFSMtWb96BbiFi mbt1hoZJANTPQ/E21byR7/bEggPnqy2O6fL886xfcO/qhEgK9RPLVMh7eCqlpQg251ww lW0w== X-Gm-Message-State: AO0yUKUYOxAZeoIm/qweiawH1VcCqTv6T9FOk6Pvuhf40GEGL7CQA82F Wntn/9YiV3Oul8Ae72wu8TiifxshZCHKJYAdGD8= X-Google-Smtp-Source: AK7set9CmbKgPSonzx8bhXpV0ku3+kFyrquqFZ97NUnME3aXD0yjnGuJ2a0KUMeOQLcSCpSUHje92w== X-Received: by 2002:a05:6870:6123:b0:177:b0ee:b034 with SMTP id s35-20020a056870612300b00177b0eeb034mr763201oae.43.1679523681375; Wed, 22 Mar 2023 15:21:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_generic_cpu_props() Date: Wed, 22 Mar 2023 19:19:58 -0300 Message-Id: <20230322222004.357013-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322222004.357013-1-dbarboza@ventanamicro.com> References: <20230322222004.357013-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679528385541100011 Content-Type: text/plain; charset="utf-8" In the process of creating the user-facing flags in register_generic_cpu_props() we're also setting default values for the cpu->cfg flags that represents MISA bits. Leaving it as is will cause a discrepancy between users of this function (at this moment the non-named CPUs) and named CPUs. Named CPUs are using set_misa() with a non-zero 'ext' value, writing cpu->cfg in the process. They'll reach riscv_cpu_realize() in a state where env->misa_ext will reflect cpu->cfg, allowing functions to choose whether to use env->misa_ext or cpu->cfg to validate MISA bits. If we guarantee that env->misa_ext will always reflect cpu->cfg at the start of riscv_cpu_realize(), functions will be able to no longer rely on cpu->cfg for MISA validation. This happens to be one blocker we have to properly support write_misa(). Sync env->misa_ext* in register_generic_cpu_props(). After that, there will be no more places where env->misa_ext needs to be sync back with cpu->cfg, so remove the now obsolete code at the end of riscv_cpu_validate_set_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d2eb2b3ba1..f1e82a8dda 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1107,14 +1107,10 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *c= pu, Error **errp) =20 /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, setting env->misa_ext and - * misa_ext_mask in the end. + * cpu->cfg accordingly. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { - CPURISCVState *env =3D &cpu->env; - uint32_t ext =3D 0; - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available @@ -1231,10 +1227,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) * validated and set everything we need. */ riscv_cpu_disable_priv_spec_isa_exts(cpu); - - ext =3D riscv_get_misa_ext_with_cpucfg(&cpu->cfg); - - env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 #ifndef CONFIG_USER_ONLY @@ -1345,6 +1337,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + /* + * This is the last point where env->misa_ext* can + * be changed. + */ if (cpu->cfg.ext_g) { riscv_cpu_enable_g(cpu, &local_err); if (local_err !=3D NULL) { @@ -1622,10 +1618,12 @@ static Property riscv_cpu_extensions[] =3D { * Register generic CPU props with user-facing flags declared * in riscv_cpu_extensions[]. * - * Note that this will overwrite existing values in cpu->cfg. + * Note that this will overwrite existing values in cpu->cfg + * and MISA. */ static void register_generic_cpu_props(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); Property *prop; DeviceState *dev =3D DEVICE(obj); =20 @@ -1636,6 +1634,10 @@ static void register_generic_cpu_props(Object *obj) #ifndef CONFIG_USER_ONLY riscv_add_satp_mode_properties(obj); #endif + + /* Keep env->misa_ext and misa_ext_mask updated */ + cpu->env.misa_ext =3D riscv_get_misa_ext_with_cpucfg(&cpu->cfg); + cpu->env.misa_ext_mask =3D cpu->env.misa_ext; } =20 static Property riscv_cpu_properties[] =3D { --=20 2.39.2