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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678812709393100001 Content-Type: text/plain; charset="utf-8" The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2752efe1eb..18032dfd4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,11 +240,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,= uint32_t ext) env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver =3D priv_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -343,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; register_cpu_props(obj); } =20 @@ -355,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -366,7 +361,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif @@ -379,7 +374,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -392,7 +387,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_g =3D true; cpu->cfg.ext_c =3D true; @@ -431,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -444,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -454,8 +449,9 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -468,7 +464,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -482,7 +478,7 @@ static void rv32_ibex_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -497,7 +493,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1160,7 +1156,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 if (priv_version >=3D PRIV_VERSION_1_10_0) { - set_priv_version(env, priv_version); + env->priv_ver =3D priv_version; } =20 /* Force disable extensions if priv spec version does not match */ --=20 2.39.2