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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678812767788100003 Content-Type: text/plain; charset="utf-8" We have all MISA specific validations in riscv_cpu_validate_misa_ext(), and we have a guarantee that env->misa_ext will always be in sync with cpu->cfg at this point during realize time, so let's convert it to use a 'misa_ext' parameter instead of reading cpu->cfg. This will prepare the function to be used in write_misa() where we won't have an updated cpu->cfg object to work with. riscv_cpu_validate_v() is changed to receive a const pointer to the cpu->cfg object via riscv_cpu_cfg(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0d8524d0d9..f8f416d6dd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -939,7 +939,8 @@ static void riscv_cpu_disas_set_info(CPUState *s, disas= semble_info *info) } } =20 -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, +static void riscv_cpu_validate_v(CPURISCVState *env, + const RISCVCPUConfig *cfg, Error **errp) { int vext_version =3D VEXT_VERSION_1_00_0; @@ -1025,46 +1026,48 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RI= SCVCPU *cpu) } } =20 -static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) + +static void riscv_cpu_validate_misa_ext(CPURISCVState *env, + uint32_t misa_ext, + Error **errp) { - CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + if (misa_ext & RVI && misa_ext & RVE) { error_setg(errp, "I and E extensions are incompatible"); return; } =20 - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + if (!(misa_ext & RVI) && !(misa_ext & RVE)) { error_setg(errp, "Either I or E extension must be set"); return; } =20 - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + if (misa_ext & RVS && !(misa_ext & RVU)) { error_setg(errp, "Setting S extension without U extension is illegal"); return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + if (misa_ext & RVH && !(misa_ext & RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers= "); return; } =20 - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + if (misa_ext & RVH && !(misa_ext & RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } =20 - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + if (misa_ext & RVD && !(misa_ext & RVF)) { error_setg(errp, "D extension requires F extension"); return; } =20 - if (cpu->cfg.ext_v) { + if (misa_ext & RVV) { /* * V depends on Zve64d, which requires D. It also * depends on Zve64f, which depends on Zve32f, @@ -1072,12 +1075,12 @@ static void riscv_cpu_validate_misa_ext(RISCVCPU *c= pu, Error **errp) * * This means that V depends on both D and F. */ - if (!(cpu->cfg.ext_d && cpu->cfg.ext_f)) { + if (!(misa_ext & RVD && misa_ext & RVF)) { error_setg(errp, "V extension requires D and F extensions"); return; } =20 - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + riscv_cpu_validate_v(env, riscv_cpu_cfg(env), &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; @@ -1331,6 +1334,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1355,7 +1359,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) riscv_set_G_virt_ext(cpu); } =20 - riscv_cpu_validate_misa_ext(cpu, &local_err); + riscv_cpu_validate_misa_ext(env, env->misa_ext, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; --=20 2.39.2