From nobody Sun May 19 09:08:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678721514; cv=none; d=zohomail.com; s=zohoarc; b=OiinwKWhkrTFI/qABVWAHzMU3MMOWFl85rnwGr7h2yBbTOgUbPdh5lrmKoml225zteTOdMbpTKeUTAvEMPvCRIhp/muWO5zfXjgvKMETqp187gKneLXzW+LgEHCoNi1ul+I04Ogt92ctgw80Uawz7DKr7eANwgeXYkTL5Yo6tc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678721514; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tgvktAzfesfxD8WUyraQcM3eJl8p+SmOjICI4meUlWI=; b=R0jNBX1Ap/Ib2+4g+GMt3RQxinYXWIMK0VYDEcGIBCfNBXl9D7JIXUATGcrcoylsAPTLcJS9ESkCBM6WbaYqP2rGi3ADD301W40EbeguRdhwXtAIEAEfUKHNHCulyRIKkUiihg1LnOh4u+JVTXRg2RzLjOSlJtheKq9nWkTvEWk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678721514581595.6819552397277; Mon, 13 Mar 2023 08:31:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pbk8L-0007Lv-HW; Mon, 13 Mar 2023 11:30:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pbk8J-0007La-Gk for qemu-devel@nongnu.org; Mon, 13 Mar 2023 11:30:43 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pbk8H-0003dD-SP for qemu-devel@nongnu.org; Mon, 13 Mar 2023 11:30:43 -0400 Received: by mail-wr1-x434.google.com with SMTP id g3so11713876wri.6 for ; Mon, 13 Mar 2023 08:30:41 -0700 (PDT) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id s11-20020a5d4ecb000000b002c70851fdd8sm8155117wrv.75.2023.03.13.08.30.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 13 Mar 2023 08:30:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678721440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tgvktAzfesfxD8WUyraQcM3eJl8p+SmOjICI4meUlWI=; b=kzaM8CL3Bv2JzTtRkdBQSzfk0m7eOfAWONTMMHd2HCls6qKe8BiCmi+pQb6G2iiczO Jd/4ZnrCZtUkAt+Z1OBiLNu3kGUCGhieVRMMPCQlNK4akr3uKNpnqj3yzTDRJEUrd/yb jOQiYxWal1QNR+KkVIrz/F+40i+BKDOpnNjRAR9RcAllx8bTHf3YDQUfAw2TVbfMghJz crJgB0UsQnDJW6Qpqki0uiaFStlwnQzTWpgeQBtL+fL057mNn4IKpOrXj/XQtMgA5NPz LX87GasE3ilXzHm68vJKBgS+mtREOixZVRw7UkHqN018eaxGhFu4idW3UCTS5UvLBlSS xlEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678721440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tgvktAzfesfxD8WUyraQcM3eJl8p+SmOjICI4meUlWI=; b=4LtynaJlWgd7gfM8tF81EfCPcc7Gb/e/5Eh3eyeXYo5yVxy1QetDkXMMaepBa9dOtc nTZpDWUTLgtDaONF1Bn3kRSCqK6CcMsIK5JdqbGwfNtr3k84URWBSYoMnHSkkt2VCJiS Hb2om7Iet9Em2o1p+CHqSjUyzeucJDYdFh8gXWwcyttC33V1gz8hH39pq7sg+H7lOZOo 7P4s6t/HbWpkCFutpT1gvFXZzbm81mZaNYf3DT6toxF/2QDMjYvycFYogNyCbw7mc1Vp O8s/glTTcbi8n67+GjeO6EapfPOrb/CXvG+G/Du/eUOMWE/trnug7WzPnqHnpS2I8I0W eRIA== X-Gm-Message-State: AO0yUKWHrvU0fR+vHgTeRNXqImwzLqkzNrpr3DLVl57miKF+CJwXdRJh 9ihoueo4B+i/OaB8alANXs0Z2Q== X-Google-Smtp-Source: AK7set8gfd9PPU4XvUUhgXt+Drxu1nsHISoUzyX7ENFSeZBF6s8WdFTdjw29C4eIOCJaz9BOhoi0/Q== X-Received: by 2002:adf:f3c5:0:b0:2cf:e6de:c6ab with SMTP id g5-20020adff3c5000000b002cfe6dec6abmr922642wrp.11.1678721440130; Mon, 13 Mar 2023 08:30:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Wei Huang , qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Ani Sinha , Peter Xu , Igor Mammedov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Roman Kapl , Brijesh Singh , David Kiarie , Jean-Philippe Brucker Subject: [PATCH 1/6] MAINTAINERS: Mark AMD-Vi emulation as orphan Date: Mon, 13 Mar 2023 16:30:26 +0100 Message-Id: <20230313153031.86107-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230313153031.86107-1-philmd@linaro.org> References: <20230313153031.86107-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678721534120100001 hw/i386/amd_iommu.c seems unmaintained: After commit 1c7955c450 ("x86-iommu: introduce parent class", 2016-07-14), almost no feature added, 2 bug fixes, other changes are generic tree-wide API cleanups. Cc: Roman Kapl Cc: Wei Huang Cc: Brijesh Singh Cc: David Kiarie Cc: Jean-Philippe Brucker Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Following https://lore.kernel.org/qemu-devel/CACGkMEtjmpX8G9HYZ0r3n5ErhAENKhQ81f4ocfC= Yrh=3DXoF=3D5hw@mail.gmail.com/ --- MAINTAINERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 95c957d587..8badbb01d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3356,6 +3356,10 @@ F: hw/i386/intel_iommu.c F: hw/i386/intel_iommu_internal.h F: include/hw/i386/intel_iommu.h =20 +AMD-Vi Emulation +S: Orphan +F: hw/i386/amd_iommu.? + OpenSBI Firmware M: Bin Meng S: Supported --=20 2.38.1 From nobody Sun May 19 09:08:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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Mon, 13 Mar 2023 08:30:45 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Wei Huang , qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Ani Sinha , Peter Xu , Igor Mammedov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/6] hw/i386/amd_iommu: Explicit use of AMDVI_BASE_ADDR in amdvi_init Date: Mon, 13 Mar 2023 16:30:27 +0100 Message-Id: <20230313153031.86107-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230313153031.86107-1-philmd@linaro.org> References: <20230313153031.86107-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678721566876100001 By accessing MemoryRegion internals, amdvi_init() gives the false idea that the PCI BAR can be modified. However this isn't true (at least the model isn't ready for that): the device is explicitly maps at the BAR at the fixed AMDVI_BASE_ADDR address in amdvi_sysbus_realize(). Since the SysBus API isn't designed to remap regions, directly use the fixed address in amdvi_init(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/amd_iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index bcd016f5c5..3813b341ec 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1519,9 +1519,9 @@ static void amdvi_init(AMDVIState *s) /* reset AMDVI specific capabilities, all r/o */ pci_set_long(s->pci.dev.config + s->capab_offset, AMDVI_CAPAB_FEATURES= ); pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, - s->mmio.addr & ~(0xffff0000)); + AMDVI_BASE_ADDR & ~(0xffff0000)); pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_HIG= H, - (s->mmio.addr & ~(0xffff)) >> 16); + (AMDVI_BASE_ADDR & ~(0xffff)) >> 16); pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_RANGE, 0xff000000); pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_MISC, 0= ); --=20 2.38.1 From nobody Sun May 19 09:08:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/6] hw/i386/amd_iommu: Remove intermediate AMDVIState::devid field Date: Mon, 13 Mar 2023 16:30:28 +0100 Message-Id: <20230313153031.86107-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230313153031.86107-1-philmd@linaro.org> References: <20230313153031.86107-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678721556785100001 AMDVIState::devid is only accessed by build_amd_iommu() which has access to the PCIDevice state. Directly get the property calling object_property_get_int() there. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/acpi-build.c | 4 +++- hw/i386/amd_iommu.c | 2 -- hw/i386/amd_iommu.h | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index ec857a117e..a27bc33956 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2395,7 +2395,9 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, /* IVHD length */ build_append_int_noprefix(table_data, ivhd_table_len, 2); /* DeviceID */ - build_append_int_noprefix(table_data, s->devid, 2); + build_append_int_noprefix(table_data, + object_property_get_int(OBJECT(&s->pci), "ad= dr", + &error_abort), 2); /* Capability offset */ build_append_int_noprefix(table_data, s->capab_offset, 2); /* IOMMU base address */ diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 3813b341ec..19f57e6318 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1513,7 +1513,6 @@ static void amdvi_init(AMDVIState *s) /* reset device ident */ pci_config_set_vendor_id(s->pci.dev.config, PCI_VENDOR_ID_AMD); pci_config_set_prog_interface(s->pci.dev.config, 00); - pci_config_set_device_id(s->pci.dev.config, s->devid); pci_config_set_class(s->pci.dev.config, 0x0806); =20 /* reset AMDVI specific capabilities, all r/o */ @@ -1581,7 +1580,6 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, AMDVI_BASE_ADDR); pci_setup_iommu(bus, amdvi_host_dma_iommu, s); - s->devid =3D object_property_get_int(OBJECT(&s->pci), "addr", &error_a= bort); msi_init(&s->pci.dev, 0, 1, true, false, errp); amdvi_init(s); } diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 79d38a3e41..5eccaad790 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -319,8 +319,6 @@ struct AMDVIState { =20 uint64_t mmio_addr; =20 - uint32_t devid; /* auto-assigned devid */ - bool enabled; /* IOMMU enabled */ bool ats_enabled; /* address translation enabled */ bool cmdbuf_enabled; /* command buffer enabled */ --=20 2.38.1 From nobody Sun May 19 09:08:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/6] hw/i386/amd_iommu: Move capab_offset from AMDVIState to AMDVIPCIState Date: Mon, 13 Mar 2023 16:30:29 +0100 Message-Id: <20230313153031.86107-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230313153031.86107-1-philmd@linaro.org> References: <20230313153031.86107-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678721525715100001 The 'PCI capability offset' is a *PCI* notion. Since AMDVIPCIState inherits PCIDevice and hold PCI-related fields, move capab_offset from AMDVIState to AMDVIPCIState. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/acpi-build.c | 2 +- hw/i386/amd_iommu.c | 14 +++++++------- hw/i386/amd_iommu.h | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index a27bc33956..7f211e1f48 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2399,7 +2399,7 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, object_property_get_int(OBJECT(&s->pci), "ad= dr", &error_abort), 2); /* Capability offset */ - build_append_int_noprefix(table_data, s->capab_offset, 2); + build_append_int_noprefix(table_data, s->pci.capab_offset, 2); /* IOMMU base address */ build_append_int_noprefix(table_data, s->mmio.addr, 8); /* PCI Segment Group */ diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 19f57e6318..9f6622e11f 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1516,15 +1516,15 @@ static void amdvi_init(AMDVIState *s) pci_config_set_class(s->pci.dev.config, 0x0806); =20 /* reset AMDVI specific capabilities, all r/o */ - pci_set_long(s->pci.dev.config + s->capab_offset, AMDVI_CAPAB_FEATURES= ); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, + pci_set_long(s->pci.dev.config + s->pci.capab_offset, AMDVI_CAPAB_FEAT= URES); + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_BAR= _LOW, AMDVI_BASE_ADDR & ~(0xffff0000)); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_HIG= H, + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_BAR= _HIGH, (AMDVI_BASE_ADDR & ~(0xffff)) >> 16); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_RANGE, + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_RAN= GE, 0xff000000); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_MISC, 0= ); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_MISC, + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_MIS= C, 0); + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_MIS= C, AMDVI_MAX_PH_ADDR | AMDVI_MAX_GVA_ADDR | AMDVI_MAX_VA_ADDR); } =20 @@ -1557,7 +1557,7 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) if (ret < 0) { return; } - s->capab_offset =3D ret; + s->pci.capab_offset =3D ret; =20 ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE, errp); diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 5eccaad790..1c0cb54bd4 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -308,6 +308,7 @@ typedef struct AMDVIAddressSpace AMDVIAddressSpace; /* functions to steal PCI config space */ typedef struct AMDVIPCIState { PCIDevice dev; /* The PCI device itself */ + uint32_t capab_offset; /* capability offset pointer */ } AMDVIPCIState; =20 struct AMDVIState { @@ -315,7 +316,6 @@ struct AMDVIState { AMDVIPCIState pci; /* IOMMU PCI device */ =20 uint32_t version; - uint32_t capab_offset; /* capability offset pointer */ =20 uint64_t mmio_addr; =20 --=20 2.38.1 From nobody Sun May 19 09:08:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/6] hw/i386/amd_iommu: Set PCI static/const fields via PCIDeviceClass Date: Mon, 13 Mar 2023 16:30:30 +0100 Message-Id: <20230313153031.86107-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230313153031.86107-1-philmd@linaro.org> References: <20230313153031.86107-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678721518505100001 Set PCI static/const fields once in amdvi_pci_class_init. They will be propagated via DeviceClassRealize handler via pci_qdev_realize() -> do_pci_register_device() -> pci_config_set*(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/amd_iommu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 9f6622e11f..8e4ce63f8e 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1511,9 +1511,7 @@ static void amdvi_init(AMDVIState *s) amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, 0x98, 0x67); =20 /* reset device ident */ - pci_config_set_vendor_id(s->pci.dev.config, PCI_VENDOR_ID_AMD); pci_config_set_prog_interface(s->pci.dev.config, 00); - pci_config_set_class(s->pci.dev.config, 0x0806); =20 /* reset AMDVI specific capabilities, all r/o */ pci_set_long(s->pci.dev.config + s->pci.capab_offset, AMDVI_CAPAB_FEAT= URES); @@ -1623,6 +1621,10 @@ static const TypeInfo amdvi_sysbus =3D { static void amdvi_pci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + + k->vendor_id =3D PCI_VENDOR_ID_AMD; + k->class_id =3D 0x0806; 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Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/6] hw/i386/amd_iommu: Factor amdvi_pci_realize out of amdvi_sysbus_realize Date: Mon, 13 Mar 2023 16:30:31 +0100 Message-Id: <20230313153031.86107-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230313153031.86107-1-philmd@linaro.org> References: <20230313153031.86107-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678721570769100001 Aside the Frankenstein model of a SysBusDevice realizing a PCIDevice, QOM parents shouldn't access children internals. In this particular case, amdvi_sysbus_realize() is just open-coding TYPE_AMD_IOMMU_PCI's DeviceRealize() handler. Factor it out. Declare QOM-cast macros with OBJECT_DECLARE_SIMPLE_TYPE() so we can cast the AMDVIPCIState in amdvi_pci_realize(). Note this commit removes the single use in the repository of pci_add_capability() and msi_init() on a *realized* QDev instance. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/i386/amd_iommu.c | 62 ++++++++++++++++++++++++++------------------- hw/i386/amd_iommu.h | 5 ++-- 2 files changed, 39 insertions(+), 28 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 8e4ce63f8e..9c77304438 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1509,20 +1509,48 @@ static void amdvi_init(AMDVIState *s) amdvi_set_quad(s, AMDVI_MMIO_EXT_FEATURES, AMDVI_EXT_FEATURES, 0xffffffffffffffef, 0); amdvi_set_quad(s, AMDVI_MMIO_STATUS, 0, 0x98, 0x67); +} + +static void amdvi_pci_realize(PCIDevice *pdev, Error **errp) +{ + AMDVIPCIState *s =3D AMD_IOMMU_PCI(pdev); + int ret; + + ret =3D pci_add_capability(pdev, AMDVI_CAPAB_ID_SEC, 0, + AMDVI_CAPAB_SIZE, errp); + if (ret < 0) { + return; + } + s->capab_offset =3D ret; + + ret =3D pci_add_capability(pdev, PCI_CAP_ID_MSI, 0, + AMDVI_CAPAB_REG_SIZE, errp); + if (ret < 0) { + return; + } + ret =3D pci_add_capability(pdev, PCI_CAP_ID_HT, 0, + AMDVI_CAPAB_REG_SIZE, errp); + if (ret < 0) { + return; + } + + if (msi_init(pdev, 0, 1, true, false, errp) < 0) { + return; + } =20 /* reset device ident */ - pci_config_set_prog_interface(s->pci.dev.config, 00); + pci_config_set_prog_interface(pdev->config, 0); =20 /* reset AMDVI specific capabilities, all r/o */ - pci_set_long(s->pci.dev.config + s->pci.capab_offset, AMDVI_CAPAB_FEAT= URES); - pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_BAR= _LOW, + pci_set_long(pdev->config + s->capab_offset, AMDVI_CAPAB_FEATURES); + pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, AMDVI_BASE_ADDR & ~(0xffff0000)); - pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_BAR= _HIGH, + pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_BAR_HIGH, (AMDVI_BASE_ADDR & ~(0xffff)) >> 16); - pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_RAN= GE, + pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_RANGE, 0xff000000); - pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_MIS= C, 0); - pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_MIS= C, + pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, 0); + pci_set_long(pdev->config + s->capab_offset + AMDVI_CAPAB_MISC, AMDVI_MAX_PH_ADDR | AMDVI_MAX_GVA_ADDR | AMDVI_MAX_VA_ADDR); } =20 @@ -1536,7 +1564,6 @@ static void amdvi_sysbus_reset(DeviceState *dev) =20 static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) { - int ret =3D 0; AMDVIState *s =3D AMD_IOMMU_DEVICE(dev); MachineState *ms =3D MACHINE(qdev_get_machine()); PCMachineState *pcms =3D PC_MACHINE(ms); @@ -1550,23 +1577,6 @@ static void amdvi_sysbus_realize(DeviceState *dev, E= rror **errp) if (!qdev_realize(DEVICE(&s->pci), &bus->qbus, errp)) { return; } - ret =3D pci_add_capability(&s->pci.dev, AMDVI_CAPAB_ID_SEC, 0, - AMDVI_CAPAB_SIZE, errp); - if (ret < 0) { - return; - } - s->pci.capab_offset =3D ret; - - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, - AMDVI_CAPAB_REG_SIZE, errp); - if (ret < 0) { - return; - } - ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_HT, 0, - AMDVI_CAPAB_REG_SIZE, errp); - if (ret < 0) { - return; - } =20 /* Pseudo address space under root PCI bus. */ x86ms->ioapic_as =3D amdvi_host_dma_iommu(bus, s, AMDVI_IOAPIC_SB_DEVI= D); @@ -1578,7 +1588,6 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio); sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, AMDVI_BASE_ADDR); pci_setup_iommu(bus, amdvi_host_dma_iommu, s); - msi_init(&s->pci.dev, 0, 1, true, false, errp); amdvi_init(s); } =20 @@ -1625,6 +1634,7 @@ static void amdvi_pci_class_init(ObjectClass *klass, = void *data) =20 k->vendor_id =3D PCI_VENDOR_ID_AMD; k->class_id =3D 0x0806; + k->realize =3D amdvi_pci_realize; =20 set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->desc =3D "AMD IOMMU (AMD-Vi) DMA Remapping device"; diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 1c0cb54bd4..6da893ee57 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -300,16 +300,17 @@ struct irte_ga { OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE) =20 #define TYPE_AMD_IOMMU_PCI "AMDVI-PCI" +OBJECT_DECLARE_SIMPLE_TYPE(AMDVIPCIState, AMD_IOMMU_PCI) =20 #define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region" =20 typedef struct AMDVIAddressSpace AMDVIAddressSpace; =20 /* functions to steal PCI config space */ -typedef struct AMDVIPCIState { +struct AMDVIPCIState { PCIDevice dev; /* The PCI device itself */ uint32_t capab_offset; /* capability offset pointer */ -} AMDVIPCIState; +}; =20 struct AMDVIState { X86IOMMUState iommu; /* IOMMU bus device */ --=20 2.38.1