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bh=iZSnZKmMJSwLI+KXTQYBAIDBbO7wyHOMhVlNhpUnus8=; b=DcN/fJ5UEsSFI8kxzTzzm1Cai7Y4lmbqkFbV0eOhk2SP8tZH6+34SJJu3nrafneEdLeUt2 xMTdArWeBxaFz2BPle+cOwYrOckfy/OsOtCczu9is/F0w6bu7Cbe2ibRGmXQe9HFg/eDIi bzqajbqLT9O5aJDQ0VNFWMMNP+WloRg= X-MC-Unique: wEW7XI9_Oz6ywxyF9FljPw-1 From: Jason Wang To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: Akihiko Odaki , Jason Wang Subject: [PULL V2 05/44] e1000: Mask registers when writing Date: Fri, 10 Mar 2023 17:34:47 +0800 Message-Id: <20230310093526.30828-6-jasowang@redhat.com> In-Reply-To: <20230310093526.30828-1-jasowang@redhat.com> References: <20230310093526.30828-1-jasowang@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1678441080931100003 Content-Type: text/plain; charset="utf-8" From: Akihiko Odaki When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki Signed-off-by: Jason Wang --- hw/net/e1000.c | 84 ++++++++++++++++++++++--------------------------------= ---- 1 file changed, 31 insertions(+), 53 deletions(-) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 9619a2e..0925a99 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -1063,30 +1063,6 @@ mac_readreg(E1000State *s, int index) } =20 static uint32_t -mac_low4_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0xf; -} - -static uint32_t -mac_low11_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0x7ff; -} - -static uint32_t -mac_low13_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0x1fff; -} - -static uint32_t -mac_low16_read(E1000State *s, int index) -{ - return s->mac_reg[index] & 0xffff; -} - -static uint32_t mac_icr_read(E1000State *s, int index) { uint32_t ret =3D s->mac_reg[ICR]; @@ -1138,11 +1114,17 @@ set_rdt(E1000State *s, int index, uint32_t val) } } =20 -static void -set_16bit(E1000State *s, int index, uint32_t val) -{ - s->mac_reg[index] =3D val & 0xffff; -} +#define LOW_BITS_SET_FUNC(num) \ + static void \ + set_##num##bit(E1000State *s, int index, uint32_t val) \ + { \ + s->mac_reg[index] =3D val & (BIT(num) - 1); \ + } + +LOW_BITS_SET_FUNC(4) +LOW_BITS_SET_FUNC(11) +LOW_BITS_SET_FUNC(13) +LOW_BITS_SET_FUNC(16) =20 static void set_dlen(E1000State *s, int index, uint32_t val) @@ -1196,7 +1178,9 @@ static const readops macreg_readops[] =3D { getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC), getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC), getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL), - getreg(GOTCL), + getreg(GOTCL), getreg(RDFH), getreg(RDFT), getreg(RDFHS), + getreg(RDFTS), getreg(RDFPC), getreg(TDFH), getreg(TDFT), + getreg(TDFHS), getreg(TDFTS), getreg(TDFPC), getreg(AIT), =20 [TOTH] =3D mac_read_clr8, [TORH] =3D mac_read_clr8, [GOTCH] =3D mac_read_clr8, [GORCH] =3D mac_read_clr8, @@ -1214,22 +1198,15 @@ static const readops macreg_readops[] =3D { [MPTC] =3D mac_read_clr4, [ICR] =3D mac_icr_read, [EECD] =3D get_eecd, [EERD] =3D flash_eerd_read, - [RDFH] =3D mac_low13_read, [RDFT] =3D mac_low13_read, - [RDFHS] =3D mac_low13_read, [RDFTS] =3D mac_low13_read, - [RDFPC] =3D mac_low13_read, - [TDFH] =3D mac_low11_read, [TDFT] =3D mac_low11_read, - [TDFHS] =3D mac_low13_read, [TDFTS] =3D mac_low13_read, - [TDFPC] =3D mac_low13_read, - [AIT] =3D mac_low16_read, =20 [CRCERRS ... MPC] =3D &mac_readreg, [IP6AT ... IP6AT + 3] =3D &mac_readreg, [IP4AT ... IP4AT + 6] =3D &= mac_readreg, - [FFLT ... FFLT + 6] =3D &mac_low11_read, + [FFLT ... FFLT + 6] =3D &mac_readreg, [RA ... RA + 31] =3D &mac_readreg, [WUPM ... WUPM + 31] =3D &mac_readreg, [MTA ... MTA + 127] =3D &mac_readreg, [VFTA ... VFTA + 127] =3D &mac_readreg, - [FFMT ... FFMT + 254] =3D &mac_low4_read, + [FFMT ... FFMT + 254] =3D &mac_readreg, [FFVT ... FFVT + 254] =3D &mac_readreg, [PBM ... PBM + 16383] =3D &mac_readreg, }; @@ -1241,26 +1218,27 @@ static const writeops macreg_writeops[] =3D { putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC), putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH), putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC), - putreg(TDFH), putreg(TDFT), putreg(TDFHS), putreg(TDFTS), - putreg(TDFPC), putreg(RDFH), putreg(RDFT), putreg(RDFHS), - putreg(RDFTS), putreg(RDFPC), putreg(IPAV), putreg(WUC), - putreg(WUS), putreg(AIT), - - [TDLEN] =3D set_dlen, [RDLEN] =3D set_dlen, [TCTL] =3D set_t= ctl, - [TDT] =3D set_tctl, [MDIC] =3D set_mdic, [ICS] =3D set_i= cs, - [TDH] =3D set_16bit, [RDH] =3D set_16bit, [RDT] =3D set_r= dt, - [IMC] =3D set_imc, [IMS] =3D set_ims, [ICR] =3D set_i= cr, - [EECD] =3D set_eecd, [RCTL] =3D set_rx_control, [CTRL] =3D set_c= trl, - [RDTR] =3D set_16bit, [RADV] =3D set_16bit, [TADV] =3D set_1= 6bit, - [ITR] =3D set_16bit, + putreg(IPAV), putreg(WUC), + putreg(WUS), + + [TDLEN] =3D set_dlen, [RDLEN] =3D set_dlen, [TCTL] =3D set_= tctl, + [TDT] =3D set_tctl, [MDIC] =3D set_mdic, [ICS] =3D set_= ics, + [TDH] =3D set_16bit, [RDH] =3D set_16bit, [RDT] =3D set_= rdt, + [IMC] =3D set_imc, [IMS] =3D set_ims, [ICR] =3D set_= icr, + [EECD] =3D set_eecd, [RCTL] =3D set_rx_control, [CTRL] =3D set_= ctrl, + [RDTR] =3D set_16bit, [RADV] =3D set_16bit, [TADV] =3D set_= 16bit, + [ITR] =3D set_16bit, [TDFH] =3D set_11bit, [TDFT] =3D set_= 11bit, + [TDFHS] =3D set_13bit, [TDFTS] =3D set_13bit, [TDFPC] =3D set_= 13bit, + [RDFH] =3D set_13bit, [RDFT] =3D set_13bit, [RDFHS] =3D set_= 13bit, + [RDFTS] =3D set_13bit, [RDFPC] =3D set_13bit, [AIT] =3D set_= 16bit, =20 [IP6AT ... IP6AT + 3] =3D &mac_writereg, [IP4AT ... IP4AT + 6] =3D &ma= c_writereg, - [FFLT ... FFLT + 6] =3D &mac_writereg, + [FFLT ... FFLT + 6] =3D &set_11bit, [RA ... RA + 31] =3D &mac_writereg, [WUPM ... WUPM + 31] =3D &mac_writereg, [MTA ... MTA + 127] =3D &mac_writereg, [VFTA ... VFTA + 127] =3D &mac_writereg, - [FFMT ... FFMT + 254] =3D &mac_writereg, [FFVT ... FFVT + 254] =3D &ma= c_writereg, + [FFMT ... FFMT + 254] =3D &set_4bit, [FFVT ... FFVT + 254] =3D &ma= c_writereg, [PBM ... PBM + 16383] =3D &mac_writereg, }; =20 --=20 2.7.4