From nobody Mon Feb 9 12:14:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678439691721589.9101243597607; Fri, 10 Mar 2023 01:14:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paYnz-0007n4-Fy; Fri, 10 Mar 2023 04:12:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paYnx-0007lQ-3p for qemu-devel@nongnu.org; Fri, 10 Mar 2023 04:12:49 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paYnq-0002aI-VM for qemu-devel@nongnu.org; Fri, 10 Mar 2023 04:12:48 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1paYne-00GpVx-8i; Fri, 10 Mar 2023 09:12:30 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org Subject: [PATCH 26/45] target/riscv: Add vaeskf1.vi decoding, translation and execution support Date: Fri, 10 Mar 2023 09:11:56 +0000 Message-Id: <20230310091215.931644-27-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk> References: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678439692158100002 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 58 ++++++++++++++++++++ target/riscv/vcrypto_helper.c | 44 +++++++++++++++ 4 files changed, 104 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 946ae8c51d..e68ced7796 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1197,3 +1197,4 @@ DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 3187c5cc64..0b3146c4f4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -937,3 +937,4 @@ vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 = @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 +vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkned.c.inc b/target/riscv/in= sn_trans/trans_rvzvkned.c.inc index 028f04a4d7..c97780f468 100644 --- a/target/riscv/insn_trans/trans_rvzvkned.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkned.c.inc @@ -97,3 +97,61 @@ GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs) + +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, VL_MULTIPLE) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (CHECK(s, a)) { \ + TCGv_ptr rd_v, rs2_v; \ + TCGv_i32 uimm_v, desc; \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + TCGLabel *vl_ok =3D gen_new_label(); = \ + TCGv_i32 tmp =3D tcg_temp_new_i32(); = \ + \ + /* save opcode for unwinding in case we throw an exception */ \ + decode_save_opc(s); \ + \ + /* check (vl % VL_MULTIPLE =3D=3D 0) assuming it's power of 2 */ = \ + tcg_gen_trunc_tl_i32(tmp, cpu_vl); \ + tcg_gen_andi_i32(tmp, tmp, VL_MULTIPLE - 1); \ + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, vl_ok); \ + gen_helper_restore_cpu_and_raise_exception(cpu_env, \ + tcg_constant_i32(RISCV_EXCP_ILLEGAL_INST)); \ + gen_set_label(vl_ok); \ + \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); = \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + uimm_v =3D tcg_constant_i32(a->rs1); = \ + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, = \ + s->cfg_ptr->vlen / 8, data)); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ + gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi * a) +{ + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D (128 / 8) && /* EGW in bytes */ + s->vstart % 4 =3D=3D 0 && + s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, 4) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 600069adb1..619e7df0fc 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -349,3 +349,47 @@ GEN_ZVKNED_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(ro= und_state); aes_inv_mix_cols(round_state);) GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(round_state, (uint8_t *)round_key);) + +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + + uimm &=3D 0b1111; + if (uimm > 10 || uimm =3D=3D 0) { + uimm ^=3D 0b1000; + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[8]; + static const uint32_t rcon[] =3D { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] =3D bswap32(vs2[i * 4 + H4(0)]); + rk[1] =3D bswap32(vs2[i * 4 + H4(1)]); + rk[2] =3D bswap32(vs2[i * 4 + H4(2)]); + rk[3] =3D bswap32(vs2[i * 4 + H4(3)]); + + rk[4] =3D rk[0] ^ (AES_Te4[(rk[3] >> 16) & 0xff] & 0xff000000) ^ + (AES_Te4[(rk[3] >> 8) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[3] >> 0) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[3] >> 24) & 0xff] & 0x000000ff) ^ rcon[uimm -= 1]; + rk[5] =3D rk[1] ^ rk[4]; + rk[6] =3D rk[2] ^ rk[5]; + rk[7] =3D rk[3] ^ rk[6]; + + vd[i * 4 + H4(0)] =3D bswap32(rk[4]); + vd[i * 4 + H4(1)] =3D bswap32(rk[5]); + vd[i * 4 + H4(2)] =3D bswap32(rk[6]); + vd[i * 4 + H4(3)] =3D bswap32(rk[7]); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} --=20 2.39.2