From nobody Tue Feb 10 03:37:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=codethink.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678439756716117.89267087646817; Fri, 10 Mar 2023 01:15:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paYo1-0007pN-Ex; Fri, 10 Mar 2023 04:12:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paYnv-0007jY-A1 for qemu-devel@nongnu.org; Fri, 10 Mar 2023 04:12:47 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paYno-0002Ze-Tv for qemu-devel@nongnu.org; Fri, 10 Mar 2023 04:12:46 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1paYnc-00GpVx-9n; Fri, 10 Mar 2023 09:12:28 +0000 From: Lawrence Hunter To: qemu-devel@nongnu.org Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk, kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, pbonzini@redhat.com, philipp.tomsich@vrull.eu, kvm@vger.kernel.org, Lawrence Hunter Subject: [PATCH 18/45] target/riscv: Add vaesef.vs decoding, translation and execution support Date: Fri, 10 Mar 2023 09:11:48 +0000 Message-Id: <20230310091215.931644-19-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk> References: <20230310091215.931644-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678439758494100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkned.c.inc | 20 +++++++++++ target/riscv/vcrypto_helper.c | 36 ++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a402bb5d40..fb30b4d13e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1189,3 +1189,4 @@ DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env= , i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) =20 DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f68025755a..5d1bb6ccc6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -929,3 +929,4 @@ vandn_vx 000001 . ..... ..... 100 ..... 1010111 = @r_vm =20 # *** RV64 Zvkned vector crypto extension *** vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkned.c.inc b/target/riscv/in= sn_trans/trans_rvzvkned.c.inc index 6f3d62bef1..69bf7f9fee 100644 --- a/target/riscv/insn_trans/trans_rvzvkned.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkned.c.inc @@ -69,4 +69,24 @@ static bool vaes_check_vv(DisasContext *s, arg_rmr *a) require_align(a->rs2, s->lmul) && s->vstart % 4 =3D=3D 0 && s->sew =3D=3D MO_32; } + +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) +{ + int8_t op_size =3D s->lmul <=3D 0 ? 1 : 1 << s->lmul; + return !is_overlapped(vd, op_size, vs2, 1); +} + +static bool vaes_check_vs(DisasContext *s, arg_rmr *a) +{ + return vaes_check_overlap(s, a->rd, a->rs2) && + MAXSZ(s) >=3D (128 / 8) && /* EGW in bytes */ + s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + s->vstart % 4 =3D=3D 0 && + s->sew =3D=3D MO_32; +} + GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index bb5ce5b50a..b079b543c7 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -214,6 +214,42 @@ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURI= SCVState *env, \ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ } =20 +#define GEN_ZVKNED_HELPER_VS(NAME, ...) \ +void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint64_t *vd =3D vd_vptr; = \ + uint64_t *vs2 =3D vs2_vptr; = \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + uint64_t round_key[2] =3D { = \ + cpu_to_le64(vs2[0]), \ + cpu_to_le64(vs2[1]), \ + }; \ + uint8_t round_state[4][4]; \ + cpu_to_le64s(vd + i * 2 + 0); \ + cpu_to_le64s(vd + i * 2 + 1); \ + for (int j =3D 0; j < 16; j++) { = \ + round_state[j / 4][j % 4] =3D ((uint8_t *)(vd + i * 2))[j]; = \ + } \ + __VA_ARGS__; \ + for (int j =3D 0; j < 16; j++) { = \ + ((uint8_t *)(vd + i * 2))[j] =3D round_state[j / 4][j % 4]; = \ + } \ + le64_to_cpus(vd + i * 2 + 0); \ + le64_to_cpus(vd + i * 2 + 1); \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ +} + GEN_ZVKNED_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state); aes_shift_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNED_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state); + aes_shift_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) --=20 2.39.2