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([2602:ae:154a:9f01:bf7f:79a0:a976:bdaf]) by smtp.gmail.com with ESMTPSA id c2-20020a170902aa4200b001991e4e0bdcsm43797plr.233.2023.03.09.12.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 12:09:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678392581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1YHQGX/lZqTZc1F+qrfJD0NpxECIkjQPgh9T1q66oi4=; b=XxbbJRvzMZSXDu19FBT2MrDsroP9xm4+voqULAneSgF0ibgZOruAFP74pOMH8lSrUs JFcdt1DCkoCwndoJorSgtyHGFlx81sS/S5nJ8sYEdz9b6vw29DQob6wefqU7OPr7Nrzh A91f0XJdO6/WdcZkyN6pmyV9pBpLEy2D4A9fDyDDlt9PStiO4hO6SSzRQoKagXDJv7iA 9gSbVjCnY1QdtGrjn0H3+3i7hcddTXYr6WV6s4Y33JMBc6QN0NGm8MeLZ/y2xR4DSv/3 zS6rCJK5n50XxCw+wkn587jTOoaRRMixWnuwhRlaMAlUUXwMBkzSJPk8DsnwBc/4GwQ5 6hZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678392581; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1YHQGX/lZqTZc1F+qrfJD0NpxECIkjQPgh9T1q66oi4=; b=7rFMy/3wG8reAdReWGFe+s6IR/9uPWyRkzVj2t1Btg9dpU89xmTrK/uorVw24iuSd4 Bb89n1G0g1zh8GrGpCqBFhcV3x5tuI9luzK2uZHO1Tj9TecvAcGdEGAR5eWbBtR7yrL7 JwTeJVaHIt75FAdOtYgWJ1AnRxvqO4mHz6biQTcAPlVOPSo0zEeZCno4lajbcyaVTZvY 6mw1gGqZ3gb+TaIPHxNIJDAbr+wKF42PbQqxOqGd+l8mQE9TKN4UYx+j5RIyi5WFlRKF CPzd/wCCbpy0G78+QZ6LWF7TCapSC20MQ+ECl4Mo1etSltTHW/JxKzi8rnQh2fEX2fl9 yLkQ== X-Gm-Message-State: AO0yUKU2kxWnPdKQWg99toCykJpfUowAShR6i2pNj/A3aAs0Xn0CKBTf V0jky8OGxfaBEubGK5MS6lVtN8bHKHwtnf16w7Y= X-Google-Smtp-Source: AK7set/H4jbEfZYCUEUBZ5BAhVvG2xgGt2mQ1FIqjTJx2fSR+3Y0YsWkstc2qbBbKtphS8mWTTtjnQ== X-Received: by 2002:a17:902:aa02:b0:19a:839d:b682 with SMTP id be2-20020a170902aa0200b0019a839db682mr20825278plb.17.1678392580986; Thu, 09 Mar 2023 12:09:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL v2 55/91] target/rx: Use cpu_psw_z as temp in flags computation Date: Thu, 9 Mar 2023 12:05:14 -0800 Message-Id: <20230309200550.3878088-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230309200550.3878088-1-richard.henderson@linaro.org> References: <20230309200550.3878088-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678393205456100001 Since PSW_Z =3D PSW_S, we can move that assignment to the end and use PSW_Z as a temporary while computing PSW_O. Use tcg_constant_i32 instead of tcg_const_i32. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/rx/translate.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 998e6e0b7e..c47aa26893 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -967,14 +967,13 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_r= r *a) /* ret =3D arg1 + arg2 + psw_c */ static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv z; - z =3D tcg_const_i32(0); + TCGv z =3D tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - tcg_gen_xor_i32(z, arg1, arg2); - tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_mov_i32(ret, cpu_psw_s); } =20 @@ -1006,13 +1005,12 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC= _mr *a) /* ret =3D arg1 + arg2 */ static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv z; - z =3D tcg_const_i32(0); + TCGv z =3D tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - tcg_gen_xor_i32(z, arg1, arg2); - tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_mov_i32(ret, cpu_psw_s); } =20 @@ -1042,23 +1040,23 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_AD= D_rrr *a) /* ret =3D arg1 - arg2 */ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv temp; tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - temp =3D tcg_temp_new_i32(); - tcg_gen_xor_i32(temp, arg1, arg2); - tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); /* CMP not required return */ if (ret) { tcg_gen_mov_i32(ret, cpu_psw_s); } } + static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) { rx_sub(NULL, arg1, arg2); } + /* ret =3D arg1 - arg2 - !psw_c */ /* -> ret =3D arg1 + ~arg2 + psw_c */ static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) --=20 2.34.1