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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 66/67] target/tricore: Avoid tcg_const_i32
Date: Tue, 7 Mar 2023 09:58:47 -0800
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All remaining uses are strictly read-only.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/tricore/translate.c | 127 +++++++++++++++++++------------------
1 file changed, 64 insertions(+), 63 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 4e3e648049..a3a5263a5d 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -124,7 +124,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int =
flags)
/* Makros for generating helpers */
=20
#define gen_helper_1arg(name, arg) do { \
- TCGv_i32 helper_tmp =3D tcg_const_i32(arg); \
+ TCGv_i32 helper_tmp =3D tcg_constant_i32(arg); \
gen_helper_##name(cpu_env, helper_tmp); \
} while (0)
=20
@@ -513,7 +513,7 @@ static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv=
r2, TCGv r3)
=20
static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_madd32_d(ret, r1, r2, temp);
}
=20
@@ -579,7 +579,7 @@ static inline void
gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_h=
igh,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
@@ -587,7 +587,7 @@ static inline void
gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_=
high,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
@@ -1224,7 +1224,7 @@ static inline void gen_msub32_d(TCGv ret, TCGv r1, TC=
Gv r2, TCGv r3)
=20
static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_msub32_d(ret, r1, r2, temp);
}
=20
@@ -1260,7 +1260,7 @@ static inline void
gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_h=
igh,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
@@ -1296,13 +1296,13 @@ static inline void
gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_=
high,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
{
- TCGv temp =3D tcg_const_i32(r2);
+ TCGv temp =3D tcg_constant_i32(r2);
gen_add_d(ret, r1, temp);
}
=20
@@ -1332,7 +1332,7 @@ static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv=
r2)
=20
static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_add_CC(ret, r1, temp);
}
=20
@@ -1364,7 +1364,7 @@ static inline void gen_addc_CC(TCGv ret, TCGv r1, TCG=
v r2)
=20
static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_addc_CC(ret, r1, temp);
}
=20
@@ -1375,7 +1375,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1=
, TCGv r2, TCGv r3,
TCGv temp2 =3D tcg_temp_new();
TCGv result =3D tcg_temp_new();
TCGv mask =3D tcg_temp_new();
- TCGv t0 =3D tcg_const_i32(0);
+ TCGv t0 =3D tcg_constant_i32(0);
=20
/* create mask for sticky bits */
tcg_gen_setcond_tl(cond, mask, r4, t0);
@@ -1404,7 +1404,7 @@ static inline void gen_cond_add(TCGCond cond, TCGv r1=
, TCGv r2, TCGv r3,
static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
TCGv r3, TCGv r4)
{
- TCGv temp =3D tcg_const_i32(r2);
+ TCGv temp =3D tcg_constant_i32(r2);
gen_cond_add(cond, r1, temp, r3, r4);
}
=20
@@ -1492,7 +1492,7 @@ static inline void gen_cond_sub(TCGCond cond, TCGv r1=
, TCGv r2, TCGv r3,
TCGv temp2 =3D tcg_temp_new();
TCGv result =3D tcg_temp_new();
TCGv mask =3D tcg_temp_new();
- TCGv t0 =3D tcg_const_i32(0);
+ TCGv t0 =3D tcg_constant_i32(0);
=20
/* create mask for sticky bits */
tcg_gen_setcond_tl(cond, mask, r4, t0);
@@ -1705,14 +1705,14 @@ gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,=
uint32_t n, uint32_t mode)
static inline void
gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
- TCGv temp =3D tcg_const_i32(n);
+ TCGv temp =3D tcg_constant_i32(n);
gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
}
=20
static inline void
gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
{
- TCGv temp =3D tcg_const_i32(n);
+ TCGv temp =3D tcg_constant_i32(n);
gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
}
=20
@@ -2149,13 +2149,13 @@ static inline void gen_absdif(TCGv ret, TCGv r1, TC=
Gv r2)
=20
static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_absdif(ret, r1, temp);
}
=20
static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
}
=20
@@ -2181,7 +2181,7 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, TC=
Gv r2)
=20
static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_mul_i32s(ret, r1, temp);
}
=20
@@ -2202,7 +2202,7 @@ static inline void gen_mul_i64s(TCGv ret_low, TCGv re=
t_high, TCGv r1, TCGv r2)
static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_mul_i64s(ret_low, ret_high, r1, temp);
}
=20
@@ -2223,31 +2223,32 @@ static inline void gen_mul_i64u(TCGv ret_low, TCGv =
ret_high, TCGv r1, TCGv r2)
static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_mul_i64u(ret_low, ret_high, r1, temp);
}
=20
static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_mul_ssov(ret, cpu_env, r1, temp);
}
=20
static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_mul_suov(ret, cpu_env, r1, temp);
}
+
/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
}
=20
static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
}
=20
@@ -2370,7 +2371,7 @@ static inline void
gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_h=
igh,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
@@ -2388,19 +2389,19 @@ static inline void
gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_=
high,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
}
=20
static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
}
=20
@@ -2418,7 +2419,7 @@ static inline void
gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_h=
igh,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
@@ -2436,7 +2437,7 @@ static inline void
gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_=
high,
int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
}
=20
@@ -2507,8 +2508,8 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shif=
t_count)
/* clear PSW.V */
tcg_gen_movi_tl(cpu_PSW_V, 0);
} else if (shift_count > 0) {
- TCGv t_max =3D tcg_const_i32(0x7FFFFFFF >> shift_count);
- TCGv t_min =3D tcg_const_i32(((int32_t) -0x80000000) >> shift_coun=
t);
+ TCGv t_max =3D tcg_constant_i32(0x7FFFFFFF >> shift_count);
+ TCGv t_min =3D tcg_constant_i32(((int32_t) -0x80000000) >> shift_c=
ount);
=20
/* calc carry */
msk_start =3D 32 - shift_count;
@@ -2546,7 +2547,7 @@ static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
=20
static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_shas(ret, r1, temp);
}
=20
@@ -2588,7 +2589,7 @@ static void gen_sh_cond(int cond, TCGv ret, TCGv r1, =
TCGv r2)
=20
static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_sh_cond(cond, ret, r1, temp);
}
=20
@@ -2599,13 +2600,13 @@ static inline void gen_adds(TCGv ret, TCGv r1, TCGv=
r2)
=20
static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_add_ssov(ret, cpu_env, r1, temp);
}
=20
static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_helper_add_suov(ret, cpu_env, r1, temp);
}
=20
@@ -2675,7 +2676,7 @@ static inline void
gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
void(*op)(TCGv, TCGv, TCGv))
{
- TCGv temp =3D tcg_const_i32(con);
+ TCGv temp =3D tcg_constant_i32(con);
gen_accumulating_cond(cond, ret, r1, temp, op);
}
=20
@@ -2842,8 +2843,8 @@ static void gen_goto_tb(DisasContext *ctx, int n, tar=
get_ulong dest)
=20
static void generate_trap(DisasContext *ctx, int class, int tin)
{
- TCGv_i32 classtemp =3D tcg_const_i32(class);
- TCGv_i32 tintemp =3D tcg_const_i32(tin);
+ TCGv_i32 classtemp =3D tcg_constant_i32(class);
+ TCGv_i32 tintemp =3D tcg_constant_i32(tin);
=20
gen_save_pc(ctx->base.pc_next);
gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
@@ -2865,7 +2866,7 @@ static inline void gen_branch_cond(DisasContext *ctx,=
TCGCond cond, TCGv r1,
static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv =
r1,
int r2, int16_t address)
{
- TCGv temp =3D tcg_const_i32(r2);
+ TCGv temp =3D tcg_constant_i32(r2);
gen_branch_cond(ctx, cond, r1, temp, address);
}
=20
@@ -3194,14 +3195,14 @@ static void decode_src_opc(DisasContext *ctx, int o=
p1)
cpu_gpr_d[15]);
break;
case OPC1_16_SRC_CMOV:
- temp =3D tcg_const_tl(0);
- temp2 =3D tcg_const_tl(const4);
+ temp =3D tcg_constant_tl(0);
+ temp2 =3D tcg_constant_tl(const4);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
break;
case OPC1_16_SRC_CMOVN:
- temp =3D tcg_const_tl(0);
- temp2 =3D tcg_const_tl(const4);
+ temp =3D tcg_constant_tl(0);
+ temp2 =3D tcg_constant_tl(const4);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
temp2, cpu_gpr_d[r1]);
break;
@@ -3267,12 +3268,12 @@ static void decode_srr_opc(DisasContext *ctx, int o=
p1)
tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC1_16_SRR_CMOV:
- temp =3D tcg_const_tl(0);
+ temp =3D tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
break;
case OPC1_16_SRR_CMOVN:
- temp =3D tcg_const_tl(0);
+ temp =3D tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
cpu_gpr_d[r2], cpu_gpr_d[r1]);
break;
@@ -3797,7 +3798,7 @@ static void decode_abs_ldw(DisasContext *ctx)
address =3D MASK_OP_ABS_OFF18(ctx->opcode);
op2 =3D MASK_OP_ABS_OP2(ctx->opcode);
=20
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
=20
switch (op2) {
case OPC2_32_ABS_LD_A:
@@ -3830,7 +3831,7 @@ static void decode_abs_ldb(DisasContext *ctx)
address =3D MASK_OP_ABS_OFF18(ctx->opcode);
op2 =3D MASK_OP_ABS_OP2(ctx->opcode);
=20
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
=20
switch (op2) {
case OPC2_32_ABS_LD_B:
@@ -3861,7 +3862,7 @@ static void decode_abs_ldst_swap(DisasContext *ctx)
address =3D MASK_OP_ABS_OFF18(ctx->opcode);
op2 =3D MASK_OP_ABS_OP2(ctx->opcode);
=20
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
=20
switch (op2) {
case OPC2_32_ABS_LDMST:
@@ -3912,7 +3913,7 @@ static void decode_abs_store(DisasContext *ctx)
address =3D MASK_OP_ABS_OFF18(ctx->opcode);
op2 =3D MASK_OP_ABS_OP2(ctx->opcode);
=20
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
=20
switch (op2) {
case OPC2_32_ABS_ST_A:
@@ -3945,7 +3946,7 @@ static void decode_abs_storeb_h(DisasContext *ctx)
address =3D MASK_OP_ABS_OFF18(ctx->opcode);
op2 =3D MASK_OP_ABS_OP2(ctx->opcode);
=20
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
=20
switch (op2) {
case OPC2_32_ABS_ST_B:
@@ -5303,7 +5304,7 @@ static void decode_rcpw_insert(DisasContext *ctx)
case OPC2_32_RCPW_INSERT:
/* if pos + width > 32 undefined result */
if (pos + width <=3D 32) {
- temp =3D tcg_const_i32(const4);
+ temp =3D tcg_constant_i32(const4);
tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, wi=
dth);
}
break;
@@ -5379,14 +5380,14 @@ static void decode_rcr_cond_select(DisasContext *ct=
x)
cpu_gpr_d[r3]);
break;
case OPC2_32_RCR_SEL:
- temp =3D tcg_const_i32(0);
- temp2 =3D tcg_const_i32(const9);
+ temp =3D tcg_constant_i32(0);
+ temp2 =3D tcg_constant_i32(const9);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
break;
case OPC2_32_RCR_SELN:
- temp =3D tcg_const_i32(0);
- temp2 =3D tcg_const_i32(const9);
+ temp =3D tcg_constant_i32(0);
+ temp2 =3D tcg_constant_i32(const9);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], temp2);
break;
@@ -6263,7 +6264,7 @@ static void decode_rr1_mul(DisasContext *ctx)
r1 =3D MASK_OP_RR1_S1(ctx->opcode);
r2 =3D MASK_OP_RR1_S2(ctx->opcode);
r3 =3D MASK_OP_RR1_D(ctx->opcode);
- n =3D tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
+ n =3D tcg_constant_i32(MASK_OP_RR1_N(ctx->opcode));
op2 =3D MASK_OP_RR1_OP2(ctx->opcode);
=20
switch (op2) {
@@ -6557,12 +6558,12 @@ static void decode_rrr_cond_select(DisasContext *ct=
x)
cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_SEL:
- temp =3D tcg_const_i32(0);
+ temp =3D tcg_constant_i32(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RRR_SELN:
- temp =3D tcg_const_i32(0);
+ temp =3D tcg_constant_i32(0);
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
@@ -7964,7 +7965,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
case OPC1_32_ABS_STOREQ:
address =3D MASK_OP_ABS_OFF18(ctx->opcode);
r1 =3D MASK_OP_ABS_S1D(ctx->opcode);
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
temp2 =3D tcg_temp_new();
=20
tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
@@ -7973,7 +7974,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
case OPC1_32_ABS_LD_Q:
address =3D MASK_OP_ABS_OFF18(ctx->opcode);
r1 =3D MASK_OP_ABS_S1D(ctx->opcode);
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
=20
tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
@@ -7989,7 +7990,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
b =3D MASK_OP_ABSB_B(ctx->opcode);
bpos =3D MASK_OP_ABSB_BPOS(ctx->opcode);
=20
- temp =3D tcg_const_i32(EA_ABS_FORMAT(address));
+ temp =3D tcg_constant_i32(EA_ABS_FORMAT(address));
temp2 =3D tcg_temp_new();
=20
tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
@@ -8116,7 +8117,7 @@ static void decode_32Bit_opc(DisasContext *ctx)
r2 =3D MASK_OP_RCRR_S3(ctx->opcode);
r3 =3D MASK_OP_RCRR_D(ctx->opcode);
const16 =3D MASK_OP_RCRR_CONST4(ctx->opcode);
- temp =3D tcg_const_i32(const16);
+ temp =3D tcg_constant_i32(const16);
temp2 =3D tcg_temp_new(); /* width*/
temp3 =3D tcg_temp_new(); /* pos */
=20
--=20
2.34.1