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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=palmer@rivosinc.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1678140501129100007 Content-Type: text/plain; charset="utf-8" From: Sunil V L Add Multiple APIC Description Table (MADT) with the RINTC structure for each cpu. Signed-off-by: Sunil V L Acked-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230302091212.999767-6-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- hw/riscv/virt-acpi-build.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index d6947fdc74..026d1eaf88 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -32,6 +32,7 @@ #include "sysemu/reset.h" #include "migration/vmstate.h" #include "hw/riscv/virt.h" +#include "hw/riscv/numa.h" =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 =20 @@ -160,6 +161,36 @@ static void build_dsdt(GArray *table_data, free_aml_allocator(); } =20 +/* + * ACPI spec, Revision 6.5+ + * 5.2.12 Multiple APIC Description Table (MADT) + * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 + * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/= view + */ +static void build_madt(GArray *table_data, + BIOSLinker *linker, + RISCVVirtState *s) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(s); + MachineState *ms =3D MACHINE(s); + const CPUArchIdList *arch_ids =3D mc->possible_cpu_arch_ids(ms); + + AcpiTable table =3D { .sig =3D "APIC", .rev =3D 6, .oem_id =3D s->oem_= id, + .oem_table_id =3D s->oem_table_id }; + + acpi_table_begin(&table, table_data); + /* Local Interrupt Controller Address */ + build_append_int_noprefix(table_data, 0, 4); + build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */ + + /* RISC-V Local INTC structures per HART */ + for (int i =3D 0; i < arch_ids->len; i++) { + riscv_acpi_madt_add_rintc(i, arch_ids, table_data); + } + + acpi_table_end(linker, &table); +} + static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) { GArray *table_offsets; @@ -181,6 +212,9 @@ static void virt_acpi_build(RISCVVirtState *s, AcpiBuil= dTables *tables) acpi_add_table(table_offsets, tables_blob); build_fadt_rev6(tables_blob, tables->linker, s, dsdt); =20 + acpi_add_table(table_offsets, tables_blob); + build_madt(tables_blob, tables->linker, s); + /* XSDT is pointed to by RSDP */ xsdt =3D tables_blob->len; build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, --=20 2.39.2