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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: [PULL 78/84] target/sparc: Avoid tcg_const_{tl,i32}
Date: Sun, 5 Mar 2023 16:39:48 -0800
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All remaining uses are strictly read-only.
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 80 +++++++++++++++++++---------------------
1 file changed, 38 insertions(+), 42 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 814f3f8b1e..5ee293326c 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -550,7 +550,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, T=
CGv src2)
if (!(env->y & 1))
T1 =3D 0;
*/
- zero =3D tcg_const_tl(0);
+ zero =3D tcg_constant_tl(0);
tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
@@ -928,8 +928,8 @@ static void gen_branch_n(DisasContext *dc, target_ulong=
pc1)
tcg_gen_mov_tl(cpu_pc, cpu_npc);
=20
tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
- t =3D tcg_const_tl(pc1);
- z =3D tcg_const_tl(0);
+ t =3D tcg_constant_tl(pc1);
+ z =3D tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc);
=20
dc->pc =3D DYNAMIC_PC;
@@ -938,9 +938,9 @@ static void gen_branch_n(DisasContext *dc, target_ulong=
pc1)
=20
static inline void gen_generic_branch(DisasContext *dc)
{
- TCGv npc0 =3D tcg_const_tl(dc->jump_pc[0]);
- TCGv npc1 =3D tcg_const_tl(dc->jump_pc[1]);
- TCGv zero =3D tcg_const_tl(0);
+ TCGv npc0 =3D tcg_constant_tl(dc->jump_pc[0]);
+ TCGv npc1 =3D tcg_constant_tl(dc->jump_pc[1]);
+ TCGv zero =3D tcg_constant_tl(0);
=20
tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1);
}
@@ -981,18 +981,14 @@ static inline void save_state(DisasContext *dc)
=20
static void gen_exception(DisasContext *dc, int which)
{
- TCGv_i32 t;
-
save_state(dc);
- t =3D tcg_const_i32(which);
- gen_helper_raise_exception(cpu_env, t);
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(which));
dc->base.is_jmp =3D DISAS_NORETURN;
}
=20
static void gen_check_align(TCGv addr, int mask)
{
- TCGv_i32 r_mask =3D tcg_const_i32(mask);
- gen_helper_check_align(cpu_env, addr, r_mask);
+ gen_helper_check_align(cpu_env, addr, tcg_constant_i32(mask));
}
=20
static inline void gen_mov_pc_npc(DisasContext *dc)
@@ -1074,7 +1070,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, =
unsigned int cond,
cmp->cond =3D logic_cond[cond];
do_compare_dst_0:
cmp->is_bool =3D false;
- cmp->c2 =3D tcg_const_tl(0);
+ cmp->c2 =3D tcg_constant_tl(0);
#ifdef TARGET_SPARC64
if (!xcc) {
cmp->c1 =3D tcg_temp_new();
@@ -1127,7 +1123,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, =
unsigned int cond,
cmp->cond =3D TCG_COND_NE;
cmp->is_bool =3D true;
cmp->c1 =3D r_dst =3D tcg_temp_new();
- cmp->c2 =3D tcg_const_tl(0);
+ cmp->c2 =3D tcg_constant_tl(0);
=20
switch (cond) {
case 0x0:
@@ -1192,7 +1188,7 @@ static void gen_fcompare(DisasCompare *cmp, unsigned =
int cc, unsigned int cond)
cmp->cond =3D TCG_COND_NE;
cmp->is_bool =3D true;
cmp->c1 =3D r_dst =3D tcg_temp_new();
- cmp->c2 =3D tcg_const_tl(0);
+ cmp->c2 =3D tcg_constant_tl(0);
=20
switch (cc) {
default:
@@ -1307,7 +1303,7 @@ static void gen_compare_reg(DisasCompare *cmp, int co=
nd, TCGv r_src)
cmp->cond =3D tcg_invert_cond(gen_tcg_cond_reg[cond]);
cmp->is_bool =3D false;
cmp->c1 =3D r_src;
- cmp->c2 =3D tcg_const_tl(0);
+ cmp->c2 =3D tcg_constant_tl(0);
}
=20
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
@@ -1908,7 +1904,7 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv=
src,
=20
static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx)
{
- TCGv m1 =3D tcg_const_tl(0xff);
+ TCGv m1 =3D tcg_constant_tl(0xff);
gen_address_mask(dc, addr);
tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB);
}
@@ -2163,8 +2159,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TC=
Gv addr,
break;
default:
{
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(memop);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(memop);
=20
save_state(dc);
#ifdef TARGET_SPARC64
@@ -2217,7 +2213,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TC=
Gv addr,
{
TCGv saddr =3D tcg_temp_new();
TCGv daddr =3D tcg_temp_new();
- TCGv four =3D tcg_const_tl(4);
+ TCGv four =3D tcg_constant_tl(4);
TCGv_i32 tmp =3D tcg_temp_new_i32();
int i;
=20
@@ -2236,8 +2232,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TC=
Gv addr,
#endif
default:
{
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(memop & MO_SIZE);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(memop & MO_SIZE);
=20
save_state(dc);
#ifdef TARGET_SPARC64
@@ -2313,15 +2309,15 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv d=
st, TCGv addr, int insn)
if (tb_cflags(dc->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
} else {
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(MO_UB);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(MO_UB);
TCGv_i64 s64, t64;
=20
save_state(dc);
t64 =3D tcg_temp_new_i64();
gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
=20
- s64 =3D tcg_const_i64(0xff);
+ s64 =3D tcg_constant_i64(0xff);
gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop);
=20
tcg_gen_trunc_i64_tl(dst, t64);
@@ -2382,7 +2378,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
=20
/* The first operation checks required alignment. */
memop =3D da.memop | MO_ALIGN_64;
- eight =3D tcg_const_tl(8);
+ eight =3D tcg_constant_tl(8);
for (i =3D 0; ; ++i) {
tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
da.mem_idx, memop);
@@ -2409,8 +2405,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
=20
default:
{
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(da.memop);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(da.memop);
=20
save_state(dc);
/* According to the table in the UA2011 manual, the only
@@ -2491,7 +2487,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
=20
/* The first operation checks required alignment. */
memop =3D da.memop | MO_ALIGN_64;
- eight =3D tcg_const_tl(8);
+ eight =3D tcg_constant_tl(8);
for (i =3D 0; ; ++i) {
tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
da.mem_idx, memop);
@@ -2566,8 +2562,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,=
int insn, int rd)
real hardware allows others. This can be seen with e.g.
FreeBSD 10.3 wrt ASI_IC_TAG. */
{
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(da.memop);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(da.memop);
TCGv_i64 tmp =3D tcg_temp_new_i64();
=20
save_state(dc);
@@ -2625,8 +2621,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T=
CGv addr,
/* ??? In theory we've handled all of the ASIs that are valid
for stda, and this should raise DAE_invalid_asi. */
{
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(da.memop);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(da.memop);
TCGv_i64 t64 =3D tcg_temp_new_i64();
=20
/* See above. */
@@ -2686,8 +2682,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,=
int insn, int rd)
break;
default:
{
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(MO_UQ);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ);
=20
save_state(dc);
gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop);
@@ -2724,7 +2720,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T=
CGv addr,
as a cacheline-style operation. */
{
TCGv d_addr =3D tcg_temp_new();
- TCGv eight =3D tcg_const_tl(8);
+ TCGv eight =3D tcg_constant_tl(8);
int i;
=20
tcg_gen_andi_tl(d_addr, addr, -8);
@@ -2736,8 +2732,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T=
CGv addr,
break;
default:
{
- TCGv_i32 r_asi =3D tcg_const_i32(da.asi);
- TCGv_i32 r_mop =3D tcg_const_i32(MO_UQ);
+ TCGv_i32 r_asi =3D tcg_constant_i32(da.asi);
+ TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ);
=20
save_state(dc);
gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop);
@@ -2786,7 +2782,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare =
*cmp, int rd, int rs)
s1 =3D gen_load_fpr_F(dc, rs);
s2 =3D gen_load_fpr_F(dc, rd);
dst =3D gen_dest_fpr_F(dc);
- zero =3D tcg_const_i32(0);
+ zero =3D tcg_constant_i32(0);
=20
tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2);
=20
@@ -3217,7 +3213,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
TCGv_i32 r_const;
=20
r_tickptr =3D tcg_temp_new_ptr();
- r_const =3D tcg_const_i32(dc->mem_idx);
+ r_const =3D tcg_constant_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
@@ -3269,7 +3265,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
TCGv_i32 r_const;
=20
r_tickptr =3D tcg_temp_new_ptr();
- r_const =3D tcg_const_i32(dc->mem_idx);
+ r_const =3D tcg_constant_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, stick));
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
@@ -3399,7 +3395,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
TCGv_i32 r_const;
=20
r_tickptr =3D tcg_temp_new_ptr();
- r_const =3D tcg_const_i32(dc->mem_idx);
+ r_const =3D tcg_constant_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
--=20
2.34.1