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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Subject: [PULL 55/84] target/sparc: Drop get_temp_tl
Date: Sun, 5 Mar 2023 16:39:25 -0800
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Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 53 ++++++++++++++--------------------------
1 file changed, 18 insertions(+), 35 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 3b0044aa66..2b4af692f6 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -85,9 +85,7 @@ typedef struct DisasContext {
uint32_t cc_op; /* current CC operation */
sparc_def_t *def;
TCGv_i32 t32[3];
- TCGv ttl[5];
int n_t32;
- int n_ttl;
#ifdef TARGET_SPARC64
int fprs_dirty;
int asi;
@@ -139,14 +137,6 @@ static inline TCGv_i32 get_temp_i32(DisasContext *dc)
return t;
}
=20
-static inline TCGv get_temp_tl(DisasContext *dc)
-{
- TCGv t;
- assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
- dc->ttl[dc->n_ttl++] =3D t =3D tcg_temp_new();
- return t;
-}
-
static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
{
#if defined(TARGET_SPARC64)
@@ -301,7 +291,7 @@ static inline TCGv gen_load_gpr(DisasContext *dc, int r=
eg)
assert(reg < 32);
return cpu_regs[reg];
} else {
- TCGv t =3D get_temp_tl(dc);
+ TCGv t =3D tcg_temp_new();
tcg_gen_movi_tl(t, 0);
return t;
}
@@ -321,7 +311,7 @@ static inline TCGv gen_dest_gpr(DisasContext *dc, int r=
eg)
assert(reg < 32);
return cpu_regs[reg];
} else {
- return get_temp_tl(dc);
+ return tcg_temp_new();
}
}
=20
@@ -2897,7 +2887,7 @@ static TCGv get_src2(DisasContext *dc, unsigned int i=
nsn)
{
if (IS_IMM) { /* immediate */
target_long simm =3D GET_FIELDs(insn, 19, 31);
- TCGv t =3D get_temp_tl(dc);
+ TCGv t =3D tcg_temp_new();
tcg_gen_movi_tl(t, simm);
return t;
} else { /* register */
@@ -3253,7 +3243,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
case 2: /* FPU & Logical Operations */
{
unsigned int xop =3D GET_FIELD(insn, 7, 12);
- TCGv cpu_dst =3D get_temp_tl(dc);
+ TCGv cpu_dst =3D tcg_temp_new();
TCGv cpu_tmp0;
=20
if (xop =3D=3D 0x3a) { /* generate trap */
@@ -3513,7 +3503,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
if (!supervisor(dc)) {
goto priv_insn;
}
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
#ifdef TARGET_SPARC64
rs1 =3D GET_FIELD(insn, 13, 17);
switch (rs1) {
@@ -4031,7 +4021,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
} else { /* register */
rs2 =3D GET_FIELD(insn, 27, 31);
cpu_src2 =3D gen_load_gpr(dc, rs2);
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
} else {
@@ -4053,7 +4043,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
} else { /* register */
rs2 =3D GET_FIELD(insn, 27, 31);
cpu_src2 =3D gen_load_gpr(dc, rs2);
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
@@ -4077,7 +4067,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
} else { /* register */
rs2 =3D GET_FIELD(insn, 27, 31);
cpu_src2 =3D gen_load_gpr(dc, rs2);
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
if (insn & (1 << 12)) {
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
@@ -4263,7 +4253,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
simm =3D GET_FIELDs(insn, 20, 31);
tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f=
);
} else { /* register */
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
@@ -4274,7 +4264,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
simm =3D GET_FIELDs(insn, 20, 31);
tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f=
);
} else { /* register */
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
@@ -4285,7 +4275,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
simm =3D GET_FIELDs(insn, 20, 31);
tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f=
);
} else { /* register */
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
@@ -4294,7 +4284,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
#endif
case 0x30:
{
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
switch(rd) {
case 0: /* wry */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src=
2);
@@ -4479,7 +4469,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
goto illegal_insn;
}
#else
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
gen_helper_wrpsr(cpu_env, cpu_tmp0);
tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
@@ -4495,7 +4485,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
{
if (!supervisor(dc))
goto priv_insn;
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
#ifdef TARGET_SPARC64
switch (rd) {
@@ -4653,7 +4643,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
CHECK_IU_FEATURE(dc, HYPV);
if (!hypervisor(dc))
goto priv_insn;
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
switch (rd) {
case 0: // hpstate
@@ -5227,7 +5217,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
} else if (xop =3D=3D 0x39) { /* V9 return */
save_state(dc);
cpu_src1 =3D get_src1(dc, insn);
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
if (IS_IMM) { /* immediate */
simm =3D GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
@@ -5249,7 +5239,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
#endif
} else {
cpu_src1 =3D get_src1(dc, insn);
- cpu_tmp0 =3D get_temp_tl(dc);
+ cpu_tmp0 =3D tcg_temp_new();
if (IS_IMM) { /* immediate */
simm =3D GET_FIELDs(insn, 19, 31);
tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm);
@@ -5344,7 +5334,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig=
ned int insn)
unsigned int xop =3D GET_FIELD(insn, 7, 12);
/* ??? gen_address_mask prevents us from using a source
register directly. Always generate a temporary. */
- TCGv cpu_addr =3D get_temp_tl(dc);
+ TCGv cpu_addr =3D tcg_temp_new();
=20
tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
if (xop =3D=3D 0x3c || xop =3D=3D 0x3e) {
@@ -5780,13 +5770,6 @@ static void disas_sparc_insn(DisasContext * dc, unsi=
gned int insn)
}
dc->n_t32 =3D 0;
}
- if (dc->n_ttl !=3D 0) {
- int i;
- for (i =3D dc->n_ttl - 1; i >=3D 0; --i) {
- tcg_temp_free(dc->ttl[i]);
- }
- dc->n_ttl =3D 0;
- }
}
=20
static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState=
*cs)
--=20
2.34.1