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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PULL 47/84] target/nios2: Drop tcg_temp_free
Date: Sun, 5 Mar 2023 16:39:17 -0800
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Translators are no longer required to free tcg temporaries.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 140bc31017..6610e22236 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -233,7 +233,6 @@ static void gen_jumpr(DisasContext *dc, int regno, bool=
is_call)
=20
tcg_gen_andi_tl(test, dest, 3);
tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l);
- tcg_temp_free(test);
=20
tcg_gen_mov_tl(cpu_pc, dest);
if (is_call) {
@@ -300,7 +299,6 @@ static void gen_ldx(DisasContext *dc, uint32_t code, ui=
nt32_t flags)
=20
tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);
- tcg_temp_free(addr);
}
=20
/* Store instructions */
@@ -312,7 +310,6 @@ static void gen_stx(DisasContext *dc, uint32_t code, ui=
nt32_t flags)
TCGv addr =3D tcg_temp_new();
tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags);
- tcg_temp_free(addr);
}
=20
/* Branch instructions */
@@ -500,7 +497,6 @@ static void eret(DisasContext *dc, uint32_t code, uint3=
2_t flags)
TCGv tmp =3D tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATU=
S]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
- tcg_temp_free(tmp);
} else {
gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_E=
A));
}
@@ -530,7 +526,6 @@ static void bret(DisasContext *dc, uint32_t code, uint3=
2_t flags)
TCGv tmp =3D tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA));
- tcg_temp_free(tmp);
=20
dc->base.is_jmp =3D DISAS_NORETURN;
#endif
@@ -597,8 +592,6 @@ static void rdctl(DisasContext *dc, uint32_t code, uint=
32_t flags)
tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDIN=
G]));
tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE=
]));
tcg_gen_and_tl(dest, t1, t2);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
break;
default:
tcg_gen_ld_tl(dest, cpu_env,
@@ -662,11 +655,9 @@ static void wrctl(DisasContext *dc, uint32_t code, uin=
t32_t flags)
tcg_gen_ld_tl(o, cpu_env, ofs);
tcg_gen_andi_tl(o, o, ro);
tcg_gen_or_tl(n, n, o);
- tcg_temp_free(o);
}
=20
tcg_gen_st_tl(n, cpu_env, ofs);
- tcg_temp_free(n);
}
break;
}
@@ -753,7 +744,6 @@ static void do_rr_mul_high(DisasContext *dc, uint32_t i=
nsn, GenFn4 *fn)
=20
fn(discard, dest_gpr(dc, instr.c),
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
- tcg_temp_free(discard);
}
=20
#define gen_rr_mul_high(fname, insn) =
\
@@ -771,7 +761,6 @@ static void do_rr_shift(DisasContext *dc, uint32_t insn=
, GenFn3 *fn)
=20
tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31);
fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), sh);
- tcg_temp_free(sh);
}
=20
#define gen_rr_shift(fname, insn) =
\
@@ -990,10 +979,6 @@ static void nios2_tr_translate_insn(DisasContextBase *=
dcbase, CPUState *cs)
=20
instr =3D &i_type_instructions[op];
instr->handler(dc, code, instr->flags);
-
- if (dc->sink) {
- tcg_temp_free(dc->sink);
- }
}
=20
static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
--=20
2.34.1