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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PULL 46/84] target/microblaze: Drop tcg_temp_free
Date: Sun, 5 Mar 2023 16:39:16 -0800
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Translators are no longer required to free tcg temporaries.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/translate.c | 54 -----------------------------------
1 file changed, 54 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 037a652cb9..eb6bdb49e1 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -104,7 +104,6 @@ static void gen_raise_exception(DisasContext *dc, uint3=
2_t index)
TCGv_i32 tmp =3D tcg_const_i32(index);
=20
gen_helper_raise_exception(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
dc->base.is_jmp =3D DISAS_NORETURN;
}
=20
@@ -119,7 +118,6 @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_=
t esr_ec)
{
TCGv_i32 tmp =3D tcg_const_i32(esr_ec);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr));
- tcg_temp_free_i32(tmp);
=20
gen_raise_exception_sync(dc, EXCP_HW_EXCP);
}
@@ -265,8 +263,6 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb *a=
rg, bool side_effects,
imm =3D tcg_const_i32(arg->imm);
=20
fn(rd, ra, imm);
-
- tcg_temp_free_i32(imm);
return true;
}
=20
@@ -312,8 +308,6 @@ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i3=
2 inb)
TCGv_i32 zero =3D tcg_const_i32(0);
=20
tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero);
-
- tcg_temp_free_i32(zero);
}
=20
/* Input and output carry. */
@@ -324,9 +318,6 @@ static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i=
32 inb)
=20
tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero);
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
-
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(zero);
}
=20
/* Input carry, but no output carry. */
@@ -361,7 +352,6 @@ static void gen_bsra(TCGv_i32 out, TCGv_i32 ina, TCGv_i=
32 inb)
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_sar_i32(out, ina, tmp);
- tcg_temp_free_i32(tmp);
}
=20
static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
@@ -369,7 +359,6 @@ static void gen_bsrl(TCGv_i32 out, TCGv_i32 ina, TCGv_i=
32 inb)
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_shr_i32(out, ina, tmp);
- tcg_temp_free_i32(tmp);
}
=20
static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
@@ -377,7 +366,6 @@ static void gen_bsll(TCGv_i32 out, TCGv_i32 ina, TCGv_i=
32 inb)
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, inb, 31);
tcg_gen_shl_i32(out, ina, tmp);
- tcg_temp_free_i32(tmp);
}
=20
static void gen_bsefi(TCGv_i32 out, TCGv_i32 ina, int32_t imm)
@@ -436,7 +424,6 @@ static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i3=
2 inb)
tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina);
tcg_gen_sub_i32(out, inb, ina);
tcg_gen_deposit_i32(out, out, lt, 31, 1);
- tcg_temp_free_i32(lt);
}
=20
static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
@@ -446,7 +433,6 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i=
32 inb)
tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina);
tcg_gen_sub_i32(out, inb, ina);
tcg_gen_deposit_i32(out, out, lt, 31, 1);
- tcg_temp_free_i32(lt);
}
=20
DO_TYPEA(cmp, false, gen_cmp)
@@ -513,21 +499,18 @@ static void gen_mulh(TCGv_i32 out, TCGv_i32 ina, TCGv=
_i32 inb)
{
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_muls2_i32(tmp, out, ina, inb);
- tcg_temp_free_i32(tmp);
}
=20
static void gen_mulhu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_mulu2_i32(tmp, out, ina, inb);
- tcg_temp_free_i32(tmp);
}
=20
static void gen_mulhsu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
{
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_mulsu2_i32(tmp, out, ina, inb);
- tcg_temp_free_i32(tmp);
}
=20
DO_TYPEA_CFG(mul, use_hw_mul, false, tcg_gen_mul_i32)
@@ -569,9 +552,6 @@ static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_=
i32 inb)
tcg_gen_not_i32(tmp, ina);
tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero);
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
-
- tcg_temp_free_i32(zero);
- tcg_temp_free_i32(tmp);
}
=20
/* No input or output carry. */
@@ -588,8 +568,6 @@ static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv=
_i32 inb)
tcg_gen_not_i32(nota, ina);
tcg_gen_add_i32(out, inb, nota);
tcg_gen_add_i32(out, out, cpu_msr_c);
-
- tcg_temp_free_i32(nota);
}
=20
DO_TYPEA(rsub, true, gen_rsub)
@@ -618,8 +596,6 @@ static void gen_src(TCGv_i32 out, TCGv_i32 ina)
tcg_gen_mov_i32(tmp, cpu_msr_c);
tcg_gen_andi_i32(cpu_msr_c, ina, 1);
tcg_gen_extract2_i32(out, ina, tmp, 1);
-
- tcg_temp_free_i32(tmp);
}
=20
static void gen_srl(TCGv_i32 out, TCGv_i32 ina)
@@ -659,7 +635,6 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, i=
nt ra, int rb)
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
tcg_gen_extu_i32_tl(ret, tmp);
- tcg_temp_free_i32(tmp);
} else if (ra) {
tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
} else if (rb) {
@@ -683,7 +658,6 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, i=
nt ra, int imm)
TCGv_i32 tmp =3D tcg_temp_new_i32();
tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
tcg_gen_extu_i32_tl(ret, tmp);
- tcg_temp_free_i32(tmp);
} else {
tcg_gen_movi_tl(ret, (uint32_t)imm);
}
@@ -772,8 +746,6 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr=
, MemOp mop,
#endif
=20
tcg_gen_qemu_ld_i32(reg_for_write(dc, rd), addr, mem_index, mop);
-
- tcg_temp_free(addr);
return true;
}
=20
@@ -879,7 +851,6 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
=20
tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
tcg_gen_mov_tl(cpu_res_addr, addr);
- tcg_temp_free(addr);
=20
if (arg->rd) {
tcg_gen_mov_i32(cpu_R[arg->rd], cpu_res_val);
@@ -925,8 +896,6 @@ static bool do_store(DisasContext *dc, int rd, TCGv add=
r, MemOp mop,
#endif
=20
tcg_gen_qemu_st_i32(reg_for_read(dc, rd), addr, mem_index, mop);
-
- tcg_temp_free(addr);
return true;
}
=20
@@ -1040,7 +1009,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar=
g)
* In either case, addr is no longer needed.
*/
tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_fail);
- tcg_temp_free(addr);
=20
/*
* Compare the value loaded during lwx with current contents of
@@ -1053,7 +1021,6 @@ static bool trans_swx(DisasContext *dc, arg_typea *ar=
g)
dc->mem_index, MO_TEUL);
=20
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
- tcg_temp_free_i32(tval);
=20
/* Success */
tcg_gen_movi_i32(cpu_msr_c, 0);
@@ -1155,8 +1122,6 @@ static bool do_bcc(DisasContext *dc, int dest_rb, int=
dest_imm,
tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget,
reg_for_read(dc, ra), zero,
cpu_btarget, next);
- tcg_temp_free_i32(zero);
- tcg_temp_free_i32(next);
=20
return true;
}
@@ -1274,7 +1239,6 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *ar=
g)
tcg_gen_st_i32(tmp_1, cpu_env,
-offsetof(MicroBlazeCPU, env)
+offsetof(CPUState, halted));
- tcg_temp_free_i32(tmp_1);
=20
tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4);
=20
@@ -1345,7 +1309,6 @@ static void msr_read(DisasContext *dc, TCGv_i32 d)
t =3D tcg_temp_new_i32();
tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC);
tcg_gen_or_i32(d, cpu_msr, t);
- tcg_temp_free_i32(t);
}
=20
static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
@@ -1442,8 +1405,6 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg)
TCGv_i32 tmp_reg =3D tcg_const_i32(arg->rs & 7);
=20
gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src);
- tcg_temp_free_i32(tmp_reg);
- tcg_temp_free_i32(tmp_ext);
}
break;
=20
@@ -1467,7 +1428,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
TCGv_i64 t64 =3D tcg_temp_new_i64();
tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
tcg_gen_extrh_i64_i32(dest, t64);
- tcg_temp_free_i64(t64);
}
return true;
#ifndef CONFIG_USER_ONLY
@@ -1498,7 +1458,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
TCGv_i64 t64 =3D tcg_temp_new_i64();
tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
tcg_gen_extrl_i64_i32(dest, t64);
- tcg_temp_free_i64(t64);
}
break;
case SR_ESR:
@@ -1532,8 +1491,6 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
TCGv_i32 tmp_reg =3D tcg_const_i32(arg->rs & 7);
=20
gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg);
- tcg_temp_free_i32(tmp_reg);
- tcg_temp_free_i32(tmp_ext);
}
break;
#endif
@@ -1559,8 +1516,6 @@ static void do_rti(DisasContext *dc)
tcg_gen_andi_i32(tmp, tmp, MSR_VM | MSR_UM);
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
-
- tcg_temp_free_i32(tmp);
}
=20
static void do_rtb(DisasContext *dc)
@@ -1571,8 +1526,6 @@ static void do_rtb(DisasContext *dc)
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_BIP));
tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
-
- tcg_temp_free_i32(tmp);
}
=20
static void do_rte(DisasContext *dc)
@@ -1584,8 +1537,6 @@ static void do_rte(DisasContext *dc)
tcg_gen_andi_i32(tmp, tmp, (MSR_VM | MSR_UM));
tcg_gen_andi_i32(cpu_msr, cpu_msr, ~(MSR_VM | MSR_UM | MSR_EIP));
tcg_gen_or_i32(cpu_msr, cpu_msr, tmp);
-
- tcg_temp_free_i32(tmp);
}
=20
/* Insns connected to FSL or AXI stream attached devices. */
@@ -1606,8 +1557,6 @@ static bool do_get(DisasContext *dc, int rd, int rb, =
int imm, int ctrl)
=20
t_ctrl =3D tcg_const_i32(ctrl);
gen_helper_get(reg_for_write(dc, rd), t_id, t_ctrl);
- tcg_temp_free_i32(t_id);
- tcg_temp_free_i32(t_ctrl);
return true;
}
=20
@@ -1638,8 +1587,6 @@ static bool do_put(DisasContext *dc, int ra, int rb, =
int imm, int ctrl)
=20
t_ctrl =3D tcg_const_i32(ctrl);
gen_helper_put(t_id, t_ctrl, reg_for_read(dc, ra));
- tcg_temp_free_i32(t_id);
- tcg_temp_free_i32(t_ctrl);
return true;
}
=20
@@ -1704,7 +1651,6 @@ static void mb_tr_translate_insn(DisasContextBase *dc=
b, CPUState *cs)
}
=20
if (dc->r0) {
- tcg_temp_free_i32(dc->r0);
dc->r0 =3D NULL;
dc->r0_set =3D false;
}
--=20
2.34.1