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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
Song Gao <gaosong@loongson.cn>
Subject: [PULL 42/84] target/loongarch: Drop tcg_temp_free
Date: Sun, 5 Mar 2023 16:39:12 -0800
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Translators are no longer required to free tcg temporaries.
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/insn_trans/trans_arith.c.inc | 12 -------
.../loongarch/insn_trans/trans_atomic.c.inc | 3 --
target/loongarch/insn_trans/trans_bit.c.inc | 12 -------
target/loongarch/insn_trans/trans_fcmp.c.inc | 3 --
.../loongarch/insn_trans/trans_fmemory.c.inc | 20 ++---------
target/loongarch/insn_trans/trans_fmov.c.inc | 6 ----
.../loongarch/insn_trans/trans_memory.c.inc | 34 +++----------------
.../insn_trans/trans_privileged.c.inc | 4 ---
target/loongarch/insn_trans/trans_shift.c.inc | 11 ------
9 files changed, 6 insertions(+), 99 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongar=
ch/insn_trans/trans_arith.c.inc
index 8e45eadbc8..43d6cf261d 100644
--- a/target/loongarch/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
@@ -100,14 +100,12 @@ static void gen_mulh_d(TCGv dest, TCGv src1, TCGv src=
2)
{
TCGv discard =3D tcg_temp_new();
tcg_gen_muls2_tl(discard, dest, src1, src2);
- tcg_temp_free(discard);
}
=20
static void gen_mulh_du(TCGv dest, TCGv src1, TCGv src2)
{
TCGv discard =3D tcg_temp_new();
tcg_gen_mulu2_tl(discard, dest, src1, src2);
- tcg_temp_free(discard);
}
=20
static void prep_divisor_d(TCGv ret, TCGv src1, TCGv src2)
@@ -129,9 +127,6 @@ static void prep_divisor_d(TCGv ret, TCGv src1, TCGv sr=
c2)
tcg_gen_and_tl(ret, ret, t0);
tcg_gen_or_tl(ret, ret, t1);
tcg_gen_movcond_tl(TCG_COND_NE, ret, ret, zero, ret, src2);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
=20
static void prep_divisor_du(TCGv ret, TCGv src2)
@@ -152,7 +147,6 @@ static void gen_div_d(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
prep_divisor_d(t0, src1, src2);
tcg_gen_div_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
@@ -160,7 +154,6 @@ static void gen_rem_d(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
prep_divisor_d(t0, src1, src2);
tcg_gen_rem_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
@@ -168,7 +161,6 @@ static void gen_div_du(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
prep_divisor_du(t0, src2);
tcg_gen_divu_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
@@ -176,7 +168,6 @@ static void gen_rem_du(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
prep_divisor_du(t0, src2);
tcg_gen_remu_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
@@ -185,7 +176,6 @@ static void gen_div_w(TCGv dest, TCGv src1, TCGv src2)
/* We need not check for integer overflow for div_w. */
prep_divisor_du(t0, src2);
tcg_gen_div_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
@@ -194,7 +184,6 @@ static void gen_rem_w(TCGv dest, TCGv src1, TCGv src2)
/* We need not check for integer overflow for rem_w. */
prep_divisor_du(t0, src2);
tcg_gen_rem_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, target_long sa)
@@ -202,7 +191,6 @@ static void gen_alsl(TCGv dest, TCGv src1, TCGv src2, t=
arget_long sa)
TCGv t0 =3D tcg_temp_new();
tcg_gen_shli_tl(t0, src1, sa);
tcg_gen_add_tl(dest, t0, src2);
- tcg_temp_free(t0);
}
=20
static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a)
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loonga=
rch/insn_trans/trans_atomic.c.inc
index 6763c1c301..612709f2a7 100644
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
@@ -14,7 +14,6 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp =
mop)
tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));
tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));
gen_set_gpr(a->rd, dest, EXT_NONE);
- tcg_temp_free(t0);
=20
return true;
}
@@ -43,8 +42,6 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp =
mop)
tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval);
gen_set_label(done);
gen_set_gpr(a->rd, dest, EXT_NONE);
- tcg_temp_free(t0);
- tcg_temp_free(val);
=20
return true;
}
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch=
/insn_trans/trans_bit.c.inc
index b01e4aeb23..25b4d7858b 100644
--- a/target/loongarch/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
@@ -122,9 +122,6 @@ static void gen_revb_2h(TCGv dest, TCGv src1)
tcg_gen_and_tl(t1, src1, mask);
tcg_gen_shli_tl(t1, t1, 8);
tcg_gen_or_tl(dest, t0, t1);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
=20
static void gen_revb_4h(TCGv dest, TCGv src1)
@@ -138,9 +135,6 @@ static void gen_revb_4h(TCGv dest, TCGv src1)
tcg_gen_and_tl(t1, src1, mask);
tcg_gen_shli_tl(t1, t1, 8);
tcg_gen_or_tl(dest, t0, t1);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
=20
static void gen_revh_2w(TCGv dest, TCGv src1)
@@ -154,9 +148,6 @@ static void gen_revh_2w(TCGv dest, TCGv src1)
tcg_gen_and_i64(t0, t0, mask);
tcg_gen_shli_i64(t1, t1, 16);
tcg_gen_or_i64(dest, t1, t0);
-
- tcg_temp_free_i64(t0);
- tcg_temp_free_i64(t1);
}
=20
static void gen_revh_d(TCGv dest, TCGv src1)
@@ -171,9 +162,6 @@ static void gen_revh_d(TCGv dest, TCGv src1)
tcg_gen_shli_tl(t0, t0, 16);
tcg_gen_or_tl(t0, t0, t1);
tcg_gen_rotri_tl(dest, t0, 32);
-
- tcg_temp_free(t0);
- tcg_temp_free(t1);
}
=20
static void gen_maskeqz(TCGv dest, TCGv src1, TCGv src2)
diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarc=
h/insn_trans/trans_fcmp.c.inc
index 2ccf646ccb..3b0da2b9f4 100644
--- a/target/loongarch/insn_trans/trans_fcmp.c.inc
+++ b/target/loongarch/insn_trans/trans_fcmp.c.inc
@@ -38,7 +38,6 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp=
_cond_s *a)
fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag=
s));
=20
tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
- tcg_temp_free(var);
return true;
}
=20
@@ -57,7 +56,5 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp=
_cond_d *a)
fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flag=
s));
=20
tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd]));
-
- tcg_temp_free(var);
return true;
}
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loong=
arch/insn_trans/trans_fmemory.c.inc
index 3025a1d3e9..0d11843873 100644
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
@@ -13,12 +13,11 @@ static void maybe_nanbox_load(TCGv freg, MemOp mop)
static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
{
TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE);
- TCGv temp =3D NULL;
=20
CHECK_FPE;
=20
if (a->imm) {
- temp =3D tcg_temp_new();
+ TCGv temp =3D tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr =3D temp;
}
@@ -26,31 +25,22 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a,=
MemOp mop)
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
=20
- if (temp) {
- tcg_temp_free(temp);
- }
-
return true;
}
=20
static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
{
TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE);
- TCGv temp =3D NULL;
=20
CHECK_FPE;
=20
if (a->imm) {
- temp =3D tcg_temp_new();
+ TCGv temp =3D tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr =3D temp;
}
=20
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
-
- if (temp) {
- tcg_temp_free(temp);
- }
return true;
}
=20
@@ -66,7 +56,6 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, Mem=
Op mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
- tcg_temp_free(addr);
=20
return true;
}
@@ -82,7 +71,6 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, Me=
mOp mop)
addr =3D tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
- tcg_temp_free(addr);
=20
return true;
}
@@ -100,7 +88,6 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, =
MemOp mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
- tcg_temp_free(addr);
=20
return true;
}
@@ -117,7 +104,6 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a=
, MemOp mop)
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
- tcg_temp_free(addr);
=20
return true;
}
@@ -135,7 +121,6 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a,=
MemOp mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
maybe_nanbox_load(cpu_fpr[a->fd], mop);
- tcg_temp_free(addr);
=20
return true;
}
@@ -152,7 +137,6 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a=
, MemOp mop)
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
- tcg_temp_free(addr);
=20
return true;
}
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarc=
h/insn_trans/trans_fmov.c.inc
index 8e5106db4e..069c941665 100644
--- a/target/loongarch/insn_trans/trans_fmov.c.inc
+++ b/target/loongarch/insn_trans/trans_fmov.c.inc
@@ -18,7 +18,6 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)
tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca]));
tcg_gen_movcond_tl(TCG_COND_EQ, cpu_fpr[a->fd], cond, zero,
cpu_fpr[a->fj], cpu_fpr[a->fk]);
- tcg_temp_free(cond);
=20
return true;
}
@@ -82,9 +81,6 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr=
2fcsr *a)
tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
tcg_gen_or_i32(fcsr0, fcsr0, temp);
tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0));
-
- tcg_temp_free_i32(temp);
- tcg_temp_free_i32(fcsr0);
}
=20
/*
@@ -134,7 +130,6 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr=
2cf *a)
t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_fpr[a->fj], 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7=
]));
- tcg_temp_free(t0);
=20
return true;
}
@@ -157,7 +152,6 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr=
2cf *a)
t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7=
]));
- tcg_temp_free(t0);
=20
return true;
}
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loonga=
rch/insn_trans/trans_memory.c.inc
index d5eb31147c..75cfdf59ad 100644
--- a/target/loongarch/insn_trans/trans_memory.c.inc
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
@@ -7,21 +7,15 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemO=
p mop)
{
TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE);
TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE);
- TCGv temp =3D NULL;
=20
if (a->imm) {
- temp =3D tcg_temp_new();
+ TCGv temp =3D tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr =3D temp;
}
=20
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
-
- if (temp) {
- tcg_temp_free(temp);
- }
-
return true;
}
=20
@@ -29,20 +23,14 @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, M=
emOp mop)
{
TCGv data =3D gpr_src(ctx, a->rd, EXT_NONE);
TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE);
- TCGv temp =3D NULL;
=20
if (a->imm) {
- temp =3D tcg_temp_new();
+ TCGv temp =3D tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr =3D temp;
}
=20
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
-
- if (temp) {
- tcg_temp_free(temp);
- }
-
return true;
}
=20
@@ -56,7 +44,6 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemO=
p mop)
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
- tcg_temp_free(addr);
=20
return true;
}
@@ -70,7 +57,6 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, Mem=
Op mop)
=20
tcg_gen_add_tl(addr, src1, src2);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
- tcg_temp_free(addr);
=20
return true;
}
@@ -146,21 +132,15 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a,=
MemOp mop)
{
TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE);
TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE);
- TCGv temp =3D NULL;
=20
if (a->imm) {
- temp =3D tcg_temp_new();
+ TCGv temp =3D tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr =3D temp;
}
=20
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
-
- if (temp) {
- tcg_temp_free(temp);
- }
-
return true;
}
=20
@@ -168,20 +148,14 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a,=
MemOp mop)
{
TCGv data =3D gpr_src(ctx, a->rd, EXT_NONE);
TCGv addr =3D gpr_src(ctx, a->rj, EXT_NONE);
- TCGv temp =3D NULL;
=20
if (a->imm) {
- temp =3D tcg_temp_new();
+ TCGv temp =3D tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr =3D temp;
}
=20
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
-
- if (temp) {
- tcg_temp_free(temp);
- }
-
return true;
}
=20
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo=
ongarch/insn_trans/trans_privileged.c.inc
index 56f4c45e09..5a04352b01 100644
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -291,10 +291,6 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrxc=
hg *a)
tcg_gen_st_tl(newv, cpu_env, csr->offset);
}
gen_set_gpr(a->rd, oldv, EXT_NONE);
-
- tcg_temp_free(temp);
- tcg_temp_free(newv);
- tcg_temp_free(oldv);
return true;
}
=20
diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongar=
ch/insn_trans/trans_shift.c.inc
index 5260af2337..bf5428a2ba 100644
--- a/target/loongarch/insn_trans/trans_shift.c.inc
+++ b/target/loongarch/insn_trans/trans_shift.c.inc
@@ -8,7 +8,6 @@ static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_shl_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
@@ -16,7 +15,6 @@ static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_shr_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
@@ -24,7 +22,6 @@ static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x1f);
tcg_gen_sar_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
@@ -32,7 +29,6 @@ static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_shl_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
@@ -40,7 +36,6 @@ static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_shr_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
@@ -48,7 +43,6 @@ static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_sar_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
@@ -64,10 +58,6 @@ static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
=20
tcg_gen_rotr_i32(t1, t1, t2);
tcg_gen_ext_i32_tl(dest, t1);
-
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
- tcg_temp_free(t0);
}
=20
static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
@@ -75,7 +65,6 @@ static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
TCGv t0 =3D tcg_temp_new();
tcg_gen_andi_tl(t0, src2, 0x3f);
tcg_gen_rotr_tl(dest, src1, t0);
- tcg_temp_free(t0);
}
=20
static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
--=20
2.34.1