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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
Song Gao <gaosong@loongson.cn>
Subject: [PULL 41/84] target/loongarch: Drop temp_new
Date: Sun, 5 Mar 2023 16:39:11 -0800
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Translators are no longer required to free tcg temporaries,
therefore there's no need to record temps for later freeing.
Replace the few uses with tcg_temp_new.
Reviewed-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/translate.h | 3 ---
target/loongarch/translate.c | 21 +++----------------
.../insn_trans/trans_privileged.c.inc | 2 +-
3 files changed, 4 insertions(+), 22 deletions(-)
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 6d2e382e8b..67bc74c05b 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -32,9 +32,6 @@ typedef struct DisasContext {
uint16_t mem_idx;
uint16_t plv;
TCGv zero;
- /* Space for 3 operands plus 1 extra for address computation. */
- TCGv temp[4];
- uint8_t ntemp;
} DisasContext;
=20
void generate_exception(DisasContext *ctx, int excp);
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 2a43ab0201..f443b5822f 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -85,9 +85,6 @@ static void loongarch_tr_init_disas_context(DisasContextB=
ase *dcbase,
bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound);
=20
- ctx->ntemp =3D 0;
- memset(ctx->temp, 0, sizeof(ctx->temp));
-
ctx->zero =3D tcg_constant_tl(0);
}
=20
@@ -110,12 +107,6 @@ static void loongarch_tr_insn_start(DisasContextBase *=
dcbase, CPUState *cs)
*
* Further, we may provide an extension for word operations.
*/
-static TCGv temp_new(DisasContext *ctx)
-{
- assert(ctx->ntemp < ARRAY_SIZE(ctx->temp));
- return ctx->temp[ctx->ntemp++] =3D tcg_temp_new();
-}
-
static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext)
{
TCGv t;
@@ -128,11 +119,11 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, D=
isasExtend src_ext)
case EXT_NONE:
return cpu_gpr[reg_num];
case EXT_SIGN:
- t =3D temp_new(ctx);
+ t =3D tcg_temp_new();
tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
return t;
case EXT_ZERO:
- t =3D temp_new(ctx);
+ t =3D tcg_temp_new();
tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
return t;
}
@@ -142,7 +133,7 @@ static TCGv gpr_src(DisasContext *ctx, int reg_num, Dis=
asExtend src_ext)
static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext)
{
if (reg_num =3D=3D 0 || dst_ext) {
- return temp_new(ctx);
+ return tcg_temp_new();
}
return cpu_gpr[reg_num];
}
@@ -195,12 +186,6 @@ static void loongarch_tr_translate_insn(DisasContextBa=
se *dcbase, CPUState *cs)
generate_exception(ctx, EXCCODE_INE);
}
=20
- for (int i =3D ctx->ntemp - 1; i >=3D 0; --i) {
- tcg_temp_free(ctx->temp[i]);
- ctx->temp[i] =3D NULL;
- }
- ctx->ntemp =3D 0;
-
ctx->base.pc_next +=3D 4;
}
=20
diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo=
ongarch/insn_trans/trans_privileged.c.inc
index 40f82becb0..56f4c45e09 100644
--- a/target/loongarch/insn_trans/trans_privileged.c.inc
+++ b/target/loongarch/insn_trans/trans_privileged.c.inc
@@ -243,7 +243,7 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
dest =3D gpr_dst(ctx, a->rd, EXT_NONE);
csr->writefn(dest, cpu_env, src1);
} else {
- dest =3D temp_new(ctx);
+ dest =3D tcg_temp_new();
tcg_gen_ld_tl(dest, cpu_env, csr->offset);
tcg_gen_st_tl(src1, cpu_env, csr->offset);
}
--=20
2.34.1