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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PULL 19/84] target/arm: Drop new_tmp_a64
Date: Sun, 5 Mar 2023 16:38:49 -0800
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This is now a simple wrapper for tcg_temp_new_i64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.h | 1 -
target/arm/tcg/translate-a64.c | 45 +++++++++++++++-------------------
target/arm/tcg/translate-sve.c | 20 +++++++--------
3 files changed, 30 insertions(+), 36 deletions(-)
diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h
index ca24c39dbe..8ac126991f 100644
--- a/target/arm/tcg/translate-a64.h
+++ b/target/arm/tcg/translate-a64.h
@@ -18,7 +18,6 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H
=20
-TCGv_i64 new_tmp_a64(DisasContext *s);
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
TCGv_i64 cpu_reg(DisasContext *s, int reg);
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index ea1f23b2e7..38804e7077 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -224,7 +224,7 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 sr=
c)
=20
TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
{
- TCGv_i64 clean =3D new_tmp_a64(s);
+ TCGv_i64 clean =3D tcg_temp_new_i64();
#ifdef CONFIG_USER_ONLY
gen_top_byte_ignore(s, clean, addr, s->tbid);
#else
@@ -269,7 +269,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, =
TCGv_i64 addr,
desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write);
desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1);
=20
- ret =3D new_tmp_a64(s);
+ ret =3D tcg_temp_new_i64();
gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
=20
return ret;
@@ -300,7 +300,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,=
bool is_write,
desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write);
desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1);
=20
- ret =3D new_tmp_a64(s);
+ ret =3D tcg_temp_new_i64();
gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr);
=20
return ret;
@@ -408,14 +408,9 @@ static void gen_goto_tb(DisasContext *s, int n, int64_=
t diff)
}
}
=20
-TCGv_i64 new_tmp_a64(DisasContext *s)
-{
- return tcg_temp_new_i64();
-}
-
TCGv_i64 new_tmp_a64_zero(DisasContext *s)
{
- TCGv_i64 t =3D new_tmp_a64(s);
+ TCGv_i64 t =3D tcg_temp_new_i64();
tcg_gen_movi_i64(t, 0);
return t;
}
@@ -456,7 +451,7 @@ TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
*/
TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
{
- TCGv_i64 v =3D new_tmp_a64(s);
+ TCGv_i64 v =3D tcg_temp_new_i64();
if (reg !=3D 31) {
if (sf) {
tcg_gen_mov_i64(v, cpu_X[reg]);
@@ -471,7 +466,7 @@ TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
=20
TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
{
- TCGv_i64 v =3D new_tmp_a64(s);
+ TCGv_i64 v =3D tcg_temp_new_i64();
if (sf) {
tcg_gen_mov_i64(v, cpu_X[reg]);
} else {
@@ -1984,7 +1979,7 @@ static void handle_sys(DisasContext *s, uint32_t insn=
, bool isread,
desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid);
desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma);
=20
- tcg_rt =3D new_tmp_a64(s);
+ tcg_rt =3D tcg_temp_new_i64();
gen_helper_mte_check_zva(tcg_rt, cpu_env,
tcg_constant_i32(desc), cpu_reg(s, rt=
));
} else {
@@ -2293,7 +2288,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3=
2_t insn)
modifier =3D new_tmp_a64_zero(s);
}
if (s->pauth_active) {
- dst =3D new_tmp_a64(s);
+ dst =3D tcg_temp_new_i64();
if (op3 =3D=3D 2) {
gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifie=
r);
} else {
@@ -2311,7 +2306,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3=
2_t insn)
if (opc =3D=3D 1) {
TCGv_i64 lr =3D cpu_reg(s, 30);
if (dst =3D=3D lr) {
- TCGv_i64 tmp =3D new_tmp_a64(s);
+ TCGv_i64 tmp =3D tcg_temp_new_i64();
tcg_gen_mov_i64(tmp, dst);
dst =3D tmp;
}
@@ -2330,7 +2325,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3=
2_t insn)
}
btype_mod =3D opc & 1;
if (s->pauth_active) {
- dst =3D new_tmp_a64(s);
+ dst =3D tcg_temp_new_i64();
modifier =3D cpu_reg_sp(s, op4);
if (op3 =3D=3D 2) {
gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
@@ -2344,7 +2339,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint3=
2_t insn)
if (opc =3D=3D 9) {
TCGv_i64 lr =3D cpu_reg(s, 30);
if (dst =3D=3D lr) {
- TCGv_i64 tmp =3D new_tmp_a64(s);
+ TCGv_i64 tmp =3D tcg_temp_new_i64();
tcg_gen_mov_i64(tmp, dst);
dst =3D tmp;
}
@@ -2912,7 +2907,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in=
sn)
=20
tcg_rt =3D cpu_reg(s, rt);
=20
- clean_addr =3D new_tmp_a64(s);
+ clean_addr =3D tcg_temp_new_i64();
gen_pc_plus_diff(s, clean_addr, imm);
if (is_vector) {
do_fp_ld(s, rt, clean_addr, size);
@@ -5167,7 +5162,7 @@ static void disas_adc_sbc(DisasContext *s, uint32_t i=
nsn)
tcg_rn =3D cpu_reg(s, rn);
=20
if (op) {
- tcg_y =3D new_tmp_a64(s);
+ tcg_y =3D tcg_temp_new_i64();
tcg_gen_not_i64(tcg_y, cpu_reg(s, rm));
} else {
tcg_y =3D cpu_reg(s, rm);
@@ -5295,7 +5290,7 @@ static void disas_cc(DisasContext *s, uint32_t insn)
=20
/* Load the arguments for the new comparison. */
if (is_imm) {
- tcg_y =3D new_tmp_a64(s);
+ tcg_y =3D tcg_temp_new_i64();
tcg_gen_movi_i64(tcg_y, y);
} else {
tcg_y =3D cpu_reg(s, y);
@@ -5724,8 +5719,8 @@ static void handle_div(DisasContext *s, bool is_signe=
d, unsigned int sf,
tcg_rd =3D cpu_reg(s, rd);
=20
if (!sf && is_signed) {
- tcg_n =3D new_tmp_a64(s);
- tcg_m =3D new_tmp_a64(s);
+ tcg_n =3D tcg_temp_new_i64();
+ tcg_m =3D tcg_temp_new_i64();
tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
} else {
@@ -5790,7 +5785,7 @@ static void handle_crc32(DisasContext *s,
default:
g_assert_not_reached();
}
- tcg_val =3D new_tmp_a64(s);
+ tcg_val =3D tcg_temp_new_i64();
tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask);
}
=20
@@ -7062,7 +7057,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i=
nt rn, int opcode,
if (itof) {
TCGv_i64 tcg_int =3D cpu_reg(s, rn);
if (!sf) {
- TCGv_i64 tcg_extend =3D new_tmp_a64(s);
+ TCGv_i64 tcg_extend =3D tcg_temp_new_i64();
=20
if (is_signed) {
tcg_gen_ext32s_i64(tcg_extend, tcg_int);
@@ -10707,8 +10702,8 @@ static void handle_vec_simd_wshli(DisasContext *s, =
bool is_q, bool is_u,
int dsize =3D 64;
int esize =3D 8 << size;
int elements =3D dsize/esize;
- TCGv_i64 tcg_rn =3D new_tmp_a64(s);
- TCGv_i64 tcg_rd =3D new_tmp_a64(s);
+ TCGv_i64 tcg_rn =3D tcg_temp_new_i64();
+ TCGv_i64 tcg_rd =3D tcg_temp_new_i64();
int i;
=20
if (size >=3D 3) {
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 718a5bce1b..2f607a355e 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4721,7 +4721,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_l=
oad *a)
return false;
}
if (sve_access_check(s)) {
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg);
@@ -4737,7 +4737,7 @@ static bool trans_LD_zpri(DisasContext *s, arg_rpri_l=
oad *a)
if (sve_access_check(s)) {
int vsz =3D vec_full_reg_size(s);
int elements =3D vsz >> dtype_esz[a->dtype];
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
=20
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn),
(a->imm * elements * (a->nreg + 1))
@@ -4840,7 +4840,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rpr=
r_load *a)
}
s->is_nonstreaming =3D true;
if (sve_access_check(s)) {
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false,
@@ -4945,7 +4945,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpr=
i_load *a)
int vsz =3D vec_full_reg_size(s);
int elements =3D vsz >> dtype_esz[a->dtype];
int off =3D (a->imm * elements) << dtype_msz(a->dtype);
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
=20
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off);
do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, 1, false,
@@ -5003,7 +5003,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rpr=
r_load *a)
}
if (sve_access_check(s)) {
int msz =3D dtype_msz(a->dtype);
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), msz);
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
do_ldrq(s, a->rd, a->pg, addr, a->dtype);
@@ -5017,7 +5017,7 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpr=
i_load *a)
return false;
}
if (sve_access_check(s)) {
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 16);
do_ldrq(s, a->rd, a->pg, addr, a->dtype);
}
@@ -5097,7 +5097,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, arg_rpr=
r_load *a)
}
s->is_nonstreaming =3D true;
if (sve_access_check(s)) {
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
do_ldro(s, a->rd, a->pg, addr, a->dtype);
@@ -5112,7 +5112,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, arg_rpr=
i_load *a)
}
s->is_nonstreaming =3D true;
if (sve_access_check(s)) {
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32);
do_ldro(s, a->rd, a->pg, addr, a->dtype);
}
@@ -5307,7 +5307,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_s=
tore *a)
return false;
}
if (sve_access_check(s)) {
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz);
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg);
@@ -5326,7 +5326,7 @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri_s=
tore *a)
if (sve_access_check(s)) {
int vsz =3D vec_full_reg_size(s);
int elements =3D vsz >> a->esz;
- TCGv_i64 addr =3D new_tmp_a64(s);
+ TCGv_i64 addr =3D tcg_temp_new_i64();
=20
tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn),
(a->imm * elements * (a->nreg + 1)) << a->msz);
--=20
2.34.1