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[77.183.4.175]) by smtp.gmail.com with ESMTPSA id j6-20020a17090686c600b008c44438734csm1993248ejy.113.2023.03.04.03.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 03:40:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677930058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Fsw6q5WagNedxBCFgTdET8uBtnuynOtVv9rkGhTlOo=; b=eD3prtXqvJmL697l2893S14PWEHhFsxhIol/mdOmUNfXdnZ/u5ThMiGTmiewZdRyfw N2Gp/m6o4rKJgtwqSKAKQc/cmxwMhczNhbtCeJQ0+6Zrbjz2HekOAI8i1ZfhTPt+YL/a W5HOLnCBBWT2s2TOgVfJdsr2dn3srfZy1eh/zl63VajEdhDbOux6hHmxy1iR5JMBcYJk KCC5WLc4rXTLIsVrTHIrbh4l+BLVI1WKd+PxqEQ2vmnvQuY0fPF3uMmmUOMVZoHPxWbD Dc1uVS3c7OtOx8nh54fd3ldcpZ1n3WQond9nOwxjaZVeXJO3ZHGt/EgDn+NqJiKdkGXV gbvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677930058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Fsw6q5WagNedxBCFgTdET8uBtnuynOtVv9rkGhTlOo=; b=cUXQXNMNA+EdCTCl8V1HL0yiXpfmqzGnvROtMjySF+B6B0safYDxfkiJxeNXDUwnjA 5Fm3eMe/b13E6haPkQ2AVpqx7cDuLILYc7gi2V/QgrpmFVgT2HMkzr2XT9Py9An2zr2q be4byqYZFwpUMjcwYGAaNKsh9dz+Y54GNMGdeXNuv80xtD0GiOLyOC4dXrw3J9sE7Kcl gULilCaN/7loC4jZz/hmig7o5IiZWFDk5d3XKdPaHzcAOqR4My/hjtU0/4tnXQ7OyhcQ kPaVaWZuLpwDv3pPS3jIQD6Kn2dD9gNIn5/tW48CabLl3NIvQF8TqUjHMbfx0T9NzJU7 6DXw== X-Gm-Message-State: AO0yUKXLscm8rmgwpBOD0BQxfs+HbNpY9Ceg7QUbGXBM+ywB5zBA+UdB mtFborzfJ6Kl878AebzDGj4BBgPszYQ= X-Google-Smtp-Source: AK7set+t3W3mIWTM7nCqTTpOv1qeB7zk8re+TJj0dtq9JQMx3bLoN5pKn1WSM8KhXMvyWWoE2cSGsA== X-Received: by 2002:a17:907:1ca3:b0:8ea:2055:4f1b with SMTP id nb35-20020a1709071ca300b008ea20554f1bmr6419058ejc.24.1677930058520; Sat, 04 Mar 2023 03:40:58 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Artyom Tarasenko , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Paul Burton , Huacai Chen , BALATON Zoltan , Jiaxun Yang , "Michael S. Tsirkin" , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH 2/5] hw/alpha/dp264: Fix wiring of PIC -> CPU interrupt Date: Sat, 4 Mar 2023 12:40:40 +0100 Message-Id: <20230304114043.121024-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304114043.121024-1-shentey@gmail.com> References: <20230304114043.121024-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=shentey@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677930151033100005 Content-Type: text/plain; charset="utf-8" Commit cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder") passes s->cpu_intr to i8259_init() in i82378_realize() directly. However, s- >cpu_intr isn't initialized yet since that happens after the south bridge's pci_realize_and_unref() in board code. Fix this by initializing s->cpu_intr before realizing the south bridge. Fixes: cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder") Signed-off-by: Bernhard Beschow --- hw/alpha/dp264.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 4161f559a7..e92295ac86 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -16,6 +16,7 @@ #include "hw/ide/pci.h" #include "hw/isa/superio.h" #include "net/net.h" +#include "qapi/error.h" #include "qemu/cutils.h" #include "qemu/datadir.h" =20 @@ -110,11 +111,12 @@ static void clipper_init(MachineState *machine) * Importantly, we need to provide a PCI device node for it, otherwise * some operating systems won't notice there's an ISA bus to configure. */ - i82378_dev =3D DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(7, 0), "i82= 378")); - isa_bus =3D ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); - + i82378_dev =3D DEVICE(pci_new(PCI_DEVFN(7, 0), "i82378")); /* Connect the ISA PIC to the Typhoon IRQ used for ISA interrupts. */ qdev_connect_gpio_out(i82378_dev, 0, isa_irq); + qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal); + + isa_bus =3D ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); =20 /* Since we have an SRM-compatible PALcode, use the SRM epoch. */ mc146818_rtc_init(isa_bus, 1900, rtc_irq); --=20 2.39.2