From nobody Mon May 6 14:13:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677930149; cv=none; d=zohomail.com; s=zohoarc; b=MYBPwf8b9mqk4sKzTyBQUyZ7nbru9ay5iI9AX9X/P/095bnTVwqnkGaQe5xM0du9XOlk9pPPfAZ/EEAoJ0J8X9z8iP1s7r8hkRknqJzxCY//ztMlnqrsrQj7AlDbBwyps6DHS7Vg48Qc0hajdwEyKJlIwl1RYzHzuRMFlH0WsDU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677930149; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=auw8G+UNlizKXHkb7A+0ZKw2fJCrhI3+d5OFW1QmeMc=; b=b0Qqsg8JBqaUYn30F13BPuCM5coCKKgoz6xedOqh4bjbWGSZeMAKLOcCD7DtX33HrkZFbuXC/TBZMbbSaAyaMUi4rW+kJdxElh2MWb4lvcU4CK40TC4DoRzRDPG5fspLQJVqkeTJmSBRq4qpNGlcOHkGg5SlMc8uR0xy/DJhbQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677930149764114.09071197854519; Sat, 4 Mar 2023 03:42:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYQGE-0003VX-8q; Sat, 04 Mar 2023 06:41:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYQG5-0003TH-OG; Sat, 04 Mar 2023 06:41:01 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYQG3-0008St-Vz; Sat, 04 Mar 2023 06:41:01 -0500 Received: by mail-ed1-x52a.google.com with SMTP id o12so20144429edb.9; Sat, 04 Mar 2023 03:40:58 -0800 (PST) Received: from Provence.localdomain (dynamic-077-183-004-175.77.183.pool.telefonica.de. [77.183.4.175]) by smtp.gmail.com with ESMTPSA id j6-20020a17090686c600b008c44438734csm1993248ejy.113.2023.03.04.03.40.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 03:40:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677930057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=auw8G+UNlizKXHkb7A+0ZKw2fJCrhI3+d5OFW1QmeMc=; b=EOqxc6X6YRqXhiRUSG1ZmYqkMoJ2wI5THCAoB32ZIDDW0ZoL8ljBWiNknsDV+OUAkE rBm5BL7D04LY4Ay12gscJtwQcn4uDHyocjStHPY2zqe5WEG7nrLFTVBnZzRNbe6a2Vh3 iuT8jfxM1XBvpHeKd+c+GhvjocB3e/qhMHXGsVikQBA622gsa+ixqY6CTDFnYzHSP622 i+CmAi57eggGa+RlLYDSlvbECv1XaVoRSGpo8aNfKqTvg5kNzg4K+Dq0Uu5QTscMWoKu /DkJrhZOmA/s2EZLjCule6OcCPyEG/FN6y3BkxVWPdCOLNjqsYjjA+hbzZKgdt0E667E ZJDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677930057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=auw8G+UNlizKXHkb7A+0ZKw2fJCrhI3+d5OFW1QmeMc=; b=xrqArD1OKD7vNVNaPiwpq/nT+fhC1NF8RsPYFeFvoPjJyAZWhTswF5HLuYRqypU6hK 6WUnv5kGBAPfzqK/3OLGdW3bpOqGErxDwH6pjk+43rHSo8us8wWwx3ANlKjx6TLoo9rn z+Ga/+KmpFnoZigLoHpMExP7RATF8xxnmW1m+CcBg4VMyfwFf7k1IYALb6S1pHM/02ek NbWcsQ4eZXiWeh2rSRgj9qg5BQ4c3eyUt7//0bFgjm3DVI90sWv/auBDwEiNamo2bU6y 9w7tX2/MeOtX6jU8fBK0OyAIfsJv+Cqat0ELYTS5cYbl8yYTWNkMrgh9gBNb2l9epoDJ TxLw== X-Gm-Message-State: AO0yUKUo6efnqGNHbPT+Pf5o+2LkfQFl/eyu1lrSKnhMtEqhSc0KU3NU Gpm+4fpI5B4Kac7oLXCfdt4uUwxrGX8= X-Google-Smtp-Source: AK7set9O3s38jTClmVaiSPY7awBwg4IbqQ40dkAg4YAe6G79BruDJrkqLtSngvF7x9z2HIsUqSM2Fg== X-Received: by 2002:a17:907:c783:b0:87d:f29:3a16 with SMTP id tz3-20020a170907c78300b0087d0f293a16mr4998405ejc.34.1677930057246; Sat, 04 Mar 2023 03:40:57 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Artyom Tarasenko , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Paul Burton , Huacai Chen , BALATON Zoltan , Jiaxun Yang , "Michael S. Tsirkin" , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH 1/5] hw/isa/vt82c686: Fix wiring of PIC -> CPU interrupt Date: Sat, 4 Mar 2023 12:40:39 +0100 Message-Id: <20230304114043.121024-2-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304114043.121024-1-shentey@gmail.com> References: <20230304114043.121024-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677930151039100006 Content-Type: text/plain; charset="utf-8" Commit bb98e0f59cde ("hw/isa/vt82c686: Remove intermediate IRQ forwarder") passes s->cpu_intr to i8259_init() in via_isa_realize() directly. However, s->cpu_intr isn't initialized yet since that happens after the south bridge's pci_realize_and_unref() in board code. Fix this by initializing s- >cpu_intr before realizing the south bridge. Fixes: bb98e0f59cde ("hw/isa/vt82c686: Remove intermediate IRQ forwarder") Signed-off-by: Bernhard Beschow --- hw/isa/vt82c686.c | 3 ++- hw/mips/fuloong2e.c | 9 +++++---- hw/ppc/pegasos2.c | 10 ++++++---- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index f4c40965cd..8900d87f59 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -578,6 +578,8 @@ static void via_isa_init(Object *obj) object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_= UHCI); object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97); object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97); + + qdev_init_gpio_out(DEVICE(obj), &s->cpu_intr, 1); } =20 static const TypeInfo via_isa_info =3D { @@ -606,7 +608,6 @@ static void via_isa_realize(PCIDevice *d, Error **errp) ISABus *isa_bus; int i; =20 - qdev_init_gpio_out(dev, &s->cpu_intr, 1); isa_bus =3D isa_bus_new(dev, pci_address_space(d), pci_address_space_i= o(d), errp); =20 diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index cfc8ca6ae4..30944f8fe7 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -295,14 +295,15 @@ static void mips_fuloong2e_init(MachineState *machine) pci_bus =3D bonito_init((qemu_irq *)&(env->irq[2])); =20 /* South bridge -> IP5 */ - pci_dev =3D pci_create_simple_multifunction(pci_bus, - PCI_DEVFN(FULOONG2E_VIA_SLOT= , 0), - true, TYPE_VT82C686B_ISA); + pci_dev =3D pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0), tr= ue, + TYPE_VT82C686B_ISA); + qdev_connect_gpio_out(DEVICE(pci_dev), 0, env->irq[5]); + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); + object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(OBJECT(pci_dev= ), "rtc"), "date"); - qdev_connect_gpio_out(DEVICE(pci_dev), 0, env->irq[5]); =20 dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); pci_ide_create_devs(PCI_DEVICE(dev)); diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 7cc375df05..b0ada9c963 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -159,13 +159,15 @@ static void pegasos2_init(MachineState *machine) pci_bus =3D mv64361_get_pci_bus(pm->mv, 1); =20 /* VIA VT8231 South Bridge (multifunction PCI device) */ - via =3D OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, = 0), - true, TYPE_VT8231_ISA)); + via =3D OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), true, + TYPE_VT8231_ISA)); + qdev_connect_gpio_out(DEVICE(via), 0, + qdev_get_gpio_in_named(pm->mv, "gpp", 31)); + pci_realize_and_unref(PCI_DEVICE(via), pci_bus, &error_fatal); + object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(via, "rtc"), "date"); - qdev_connect_gpio_out(DEVICE(via), 0, - qdev_get_gpio_in_named(pm->mv, "gpp", 31)); =20 dev =3D PCI_DEVICE(object_resolve_path_component(via, "ide")); pci_ide_create_devs(dev); --=20 2.39.2 From nobody Mon May 6 14:13:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677930150; cv=none; d=zohomail.com; s=zohoarc; b=aNWyeqlnSV6Ia6uHkXQ64kv1dgbM9LJbcR8QaGCQf5OIS/DCK4ywTJ/Ebj1N81EIOf7QG8KbmqTI6TLGoGDwHCqxx27h56VY287eV7z5KFI3QF43dHgb4yj++3IgRRkae75Ke0PUysgDSxnF07aCRbW45k0tDT1ImXw/Vg9W7R0= ARC-Message-Signature: i=1; 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[77.183.4.175]) by smtp.gmail.com with ESMTPSA id j6-20020a17090686c600b008c44438734csm1993248ejy.113.2023.03.04.03.40.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 03:40:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677930058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Fsw6q5WagNedxBCFgTdET8uBtnuynOtVv9rkGhTlOo=; b=eD3prtXqvJmL697l2893S14PWEHhFsxhIol/mdOmUNfXdnZ/u5ThMiGTmiewZdRyfw N2Gp/m6o4rKJgtwqSKAKQc/cmxwMhczNhbtCeJQ0+6Zrbjz2HekOAI8i1ZfhTPt+YL/a W5HOLnCBBWT2s2TOgVfJdsr2dn3srfZy1eh/zl63VajEdhDbOux6hHmxy1iR5JMBcYJk KCC5WLc4rXTLIsVrTHIrbh4l+BLVI1WKd+PxqEQ2vmnvQuY0fPF3uMmmUOMVZoHPxWbD Dc1uVS3c7OtOx8nh54fd3ldcpZ1n3WQond9nOwxjaZVeXJO3ZHGt/EgDn+NqJiKdkGXV gbvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677930058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Fsw6q5WagNedxBCFgTdET8uBtnuynOtVv9rkGhTlOo=; b=cUXQXNMNA+EdCTCl8V1HL0yiXpfmqzGnvROtMjySF+B6B0safYDxfkiJxeNXDUwnjA 5Fm3eMe/b13E6haPkQ2AVpqx7cDuLILYc7gi2V/QgrpmFVgT2HMkzr2XT9Py9An2zr2q be4byqYZFwpUMjcwYGAaNKsh9dz+Y54GNMGdeXNuv80xtD0GiOLyOC4dXrw3J9sE7Kcl gULilCaN/7loC4jZz/hmig7o5IiZWFDk5d3XKdPaHzcAOqR4My/hjtU0/4tnXQ7OyhcQ kPaVaWZuLpwDv3pPS3jIQD6Kn2dD9gNIn5/tW48CabLl3NIvQF8TqUjHMbfx0T9NzJU7 6DXw== X-Gm-Message-State: AO0yUKXLscm8rmgwpBOD0BQxfs+HbNpY9Ceg7QUbGXBM+ywB5zBA+UdB mtFborzfJ6Kl878AebzDGj4BBgPszYQ= X-Google-Smtp-Source: AK7set+t3W3mIWTM7nCqTTpOv1qeB7zk8re+TJj0dtq9JQMx3bLoN5pKn1WSM8KhXMvyWWoE2cSGsA== X-Received: by 2002:a17:907:1ca3:b0:8ea:2055:4f1b with SMTP id nb35-20020a1709071ca300b008ea20554f1bmr6419058ejc.24.1677930058520; Sat, 04 Mar 2023 03:40:58 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Artyom Tarasenko , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Paul Burton , Huacai Chen , BALATON Zoltan , Jiaxun Yang , "Michael S. Tsirkin" , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH 2/5] hw/alpha/dp264: Fix wiring of PIC -> CPU interrupt Date: Sat, 4 Mar 2023 12:40:40 +0100 Message-Id: <20230304114043.121024-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304114043.121024-1-shentey@gmail.com> References: <20230304114043.121024-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=shentey@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677930151033100005 Content-Type: text/plain; charset="utf-8" Commit cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder") passes s->cpu_intr to i8259_init() in i82378_realize() directly. However, s- >cpu_intr isn't initialized yet since that happens after the south bridge's pci_realize_and_unref() in board code. Fix this by initializing s->cpu_intr before realizing the south bridge. Fixes: cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder") Signed-off-by: Bernhard Beschow --- hw/alpha/dp264.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 4161f559a7..e92295ac86 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -16,6 +16,7 @@ #include "hw/ide/pci.h" #include "hw/isa/superio.h" #include "net/net.h" +#include "qapi/error.h" #include "qemu/cutils.h" #include "qemu/datadir.h" =20 @@ -110,11 +111,12 @@ static void clipper_init(MachineState *machine) * Importantly, we need to provide a PCI device node for it, otherwise * some operating systems won't notice there's an ISA bus to configure. */ - i82378_dev =3D DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(7, 0), "i82= 378")); - isa_bus =3D ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); - + i82378_dev =3D DEVICE(pci_new(PCI_DEVFN(7, 0), "i82378")); /* Connect the ISA PIC to the Typhoon IRQ used for ISA interrupts. */ qdev_connect_gpio_out(i82378_dev, 0, isa_irq); + qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal); + + isa_bus =3D ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); =20 /* Since we have an SRM-compatible PALcode, use the SRM epoch. */ mc146818_rtc_init(isa_bus, 1900, rtc_irq); --=20 2.39.2 From nobody Mon May 6 14:13:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677930114; cv=none; d=zohomail.com; s=zohoarc; b=YSbD5iON4275rcTv1v2xTv5dIexno0CU2Yl1CkVbt+6oOP5N1STgoChHXRA8bXkYt6TEf/q3vnT0JPVc6b7FdN/bwayn+1sQiRbEAOcMum4XEBHbQ0P0M2AJrg9SqUWpVAt/BATKq8Wp+AKLKBXs9dftRyMK3ujZhUzZ8EG36KU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677930114; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=if4VvV49pa65j5fAVPx4ylF15nZ6C4JQhn8tvZ+BbSo=; b=BLUPn61guXq4tGiuIwpTVc4VxPXj9QH9iMjU2Tw2VHijMdUD2msUuhUCYoVY6ZX/XxMnKum86GHSDR+X3JpGRGoEs9jxn/kzK1cDEbHe+HNVj1HRfbBiwGFCkipJHE2D3NUIj4xOOPipI6GfybCiLdYBau317dDTR5kM/fsqvdA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16779301149024.234931688596589; Sat, 4 Mar 2023 03:41:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYQGG-0003WE-I6; Sat, 04 Mar 2023 06:41:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYQG7-0003Tg-A1; Sat, 04 Mar 2023 06:41:03 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYQG5-0008Ta-MI; Sat, 04 Mar 2023 06:41:02 -0500 Received: by mail-ed1-x532.google.com with SMTP id da10so20288194edb.3; Sat, 04 Mar 2023 03:41:00 -0800 (PST) Received: from Provence.localdomain (dynamic-077-183-004-175.77.183.pool.telefonica.de. [77.183.4.175]) by smtp.gmail.com with ESMTPSA id j6-20020a17090686c600b008c44438734csm1993248ejy.113.2023.03.04.03.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 03:40:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677930060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=if4VvV49pa65j5fAVPx4ylF15nZ6C4JQhn8tvZ+BbSo=; b=GaTd50DqLAMS5/uiGPkZHnVipHuUF3ZKS3yT5UOTHf8BwgPjwLpOl/DOkn7TLi9NMH 7MkU/kmcI7D0moUdyCVrJE7VMwZju4WRAYQd1tnJp1j2JOHk2cnB+l5tz5ZpJd8Sekbm wzFycyS8pKJx/tQNohH31PiUtq0cCPlRT7HfMXiR1kP3QOnwH5fQV4ihChBac4Og5x8y I+AHkCXcoHJKBFExwKbj+THetR8akRl6bnXv2BW3GOVepxPq/bYkdgJGGLGzX7AVACTf +JjWzl5y2MFDbmv6fA4TkC58F92+O2Wcxq/9KaWdJYDV7KYAZ2AmmSrzy7fAVd7/CGoj Wt6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677930060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=if4VvV49pa65j5fAVPx4ylF15nZ6C4JQhn8tvZ+BbSo=; b=6B6B1QFolINqVY9jAqKrf8XesGqMHSOeRIAbmA/HFLqNh6inH0AYDt1dFk32d0C47M pXtTLGrIaDYtUFqtvg84tmkrxJmdMq5wJVylkcAQ6Txo4rASVewMqYerLHKTZtTk6Km+ Rz6ettkCSMkUFD54Uz4qUrFnUViLWF9TEFU2kWDERxSc7+sQJAVOBANzFBUIORMQJwX8 DKDxaWkXlf73lH6L97ay5TN+ObQ24Pye37M4jT2CO1KnEia0m4m/OI+Q6xrmToUa3aJ6 zvcpfbGUb9kARzXvMW0bATnfVqu+Ec7MgerWOJnSm152O6RN2ezxRyjMrtiSv2atf8oW iPsA== X-Gm-Message-State: AO0yUKXv+2CSPSZdGkGEJKnQg8/Dm2En92wluQUc1/3V1aT1jO+UQrjF xKsTRi2vUqo0WTUPwEJSY7IS2EnUFtk= X-Google-Smtp-Source: AK7set94ggGB50sJdeeFyDyuRkjRCo2jFoB2YwGLJM+vjrqDsQRnNCJ2LduNCPz3F96cy8ODlIc5Aw== X-Received: by 2002:a17:907:7b8d:b0:8b2:c26c:369e with SMTP id ne13-20020a1709077b8d00b008b2c26c369emr5772756ejc.76.1677930059749; Sat, 04 Mar 2023 03:40:59 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Artyom Tarasenko , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Paul Burton , Huacai Chen , BALATON Zoltan , Jiaxun Yang , "Michael S. Tsirkin" , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH 3/5] hw/ppc/prep: Fix wiring of PIC -> CPU interrupt Date: Sat, 4 Mar 2023 12:40:41 +0100 Message-Id: <20230304114043.121024-4-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304114043.121024-1-shentey@gmail.com> References: <20230304114043.121024-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=shentey@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677930116843100003 Content-Type: text/plain; charset="utf-8" Commit cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder") passes s->cpu_intr to i8259_init() in i82378_realize() directly. However, s- >cpu_intr isn't initialized yet since that happens after the south bridge's pci_realize_and_unref() in board code. Fix this by initializing s->cpu_intr before realizing the south bridge. Fixes: cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder") Signed-off-by: Bernhard Beschow Reviewed-by: Daniel Henrique Barboza --- hw/ppc/prep.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index d00280c0f8..cfa47c1e44 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -270,9 +270,11 @@ static void ibm_40p_init(MachineState *machine) } =20 /* PCI -> ISA bridge */ - i82378_dev =3D DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i8= 2378")); + i82378_dev =3D DEVICE(pci_new(PCI_DEVFN(11, 0), "i82378")); qdev_connect_gpio_out(i82378_dev, 0, qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); + qdev_realize_and_unref(i82378_dev, BUS(pci_bus), &error_fatal); + sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15)); isa_bus =3D ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); =20 --=20 2.39.2 From nobody Mon May 6 14:13:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677930108; cv=none; d=zohomail.com; s=zohoarc; b=BjUIUWGdfZz52Et7HEYYt480WcTKj6+0rNYKNfSiIH8QeBTSFWvTeTKX1rg1xdYAmBw8OBDrkblL4JDcdRM035ZWoQ+MdSHf+cOiAmLsk8tPSRtJdbixSmmzkWw5WUQm3c0HRfClF0+TdGg3GFZCa10io3wXGI0s4ep2N0a6x6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677930108; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bdYaBxCISe0pefR1i+qWPkcMEXBRaMVRlBH94wLysTs=; b=fk+Mc2JkeBCbPodefVzHPUl709EcSZc6cIy+AswmG5zRHuflwmerSrQdaospBK1vDmqQumE2zb6G7QMCiMgDN1eF6+37XhM2BNBa22Cjq010ulH2m437YjBpPTldz9sgzHHco8fq9TxsyzPhvh3CCCLZxSeYKxL9X9P8sKA5FYg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167793010863990.62848773866347; Sat, 4 Mar 2023 03:41:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYQGJ-0003Yv-Gm; Sat, 04 Mar 2023 06:41:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYQG8-0003Tz-Q5; Sat, 04 Mar 2023 06:41:05 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYQG6-0008U5-VW; Sat, 04 Mar 2023 06:41:04 -0500 Received: by mail-ed1-x532.google.com with SMTP id i34so20189555eda.7; Sat, 04 Mar 2023 03:41:02 -0800 (PST) Received: from Provence.localdomain (dynamic-077-183-004-175.77.183.pool.telefonica.de. [77.183.4.175]) by smtp.gmail.com with ESMTPSA id j6-20020a17090686c600b008c44438734csm1993248ejy.113.2023.03.04.03.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 03:41:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677930061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bdYaBxCISe0pefR1i+qWPkcMEXBRaMVRlBH94wLysTs=; b=my4c3hrZP6CfRndcV2FuY/3sZURSrgfAZ7yneeMLc/QUL3fZuz6tgsrc4w2Av3SRk5 67B0d/yOYJOzoBPvhn46LmB0qg9OOTDo7i3NeMOn+pKFkPu1BnAaqOKXsxKxk2VLwC4Q NuYsIgrYP7XPN92OxCrDYXB3X3w/R5V9FaUcIiMQiVInfitCe6urwY1QJ7uVTFNETVm+ s2KhTbXgA1UdBqF1/mWXh9bxEAwalnQrOKLiQ0NafrPPElr6S1VBG/sP/kxQApU1FF3W 31U6WUlru9qw1Akr0AXZ/rE7uD5LQ6HBSN17i6Rl4y7mBl/x8e8uabE2UIZxRs+IDAR7 U1Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677930061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bdYaBxCISe0pefR1i+qWPkcMEXBRaMVRlBH94wLysTs=; b=Of9YKsq7bqRxjdI3HUm4ZVZ2xmhhysp20EShnvcDRFck/y8ejRwWC5r2Q/3+dHV5er E9jej2QIioduJ8Tgif5SQ88CZ/RvwqGvThWPZRnZve3ZY92ddtC78sbbVnd5sHtXyX60 cx8Qdvi/P3+RzRU9UA2yuW5nNOySG605YH+yeCb2epSqAgVC0ktVadg+fOTvvHZcH/bA T3jbs8PX/WAWfct5uaLfbNGXApze1vKWD+9vK6EwWxEYnqxd8pKQq3oFaHKYXBhixgNv ZiJg2gSSW8s12L7XlxRzHo6uVIggaCz99ZGpAqUWm5tykIpeoICDXGKQ6UvkuBNfckNZ FZOA== X-Gm-Message-State: AO0yUKX41mTPB8PXPXHdctKvgLu4mPGr3O5rhOv+0aH4frIm96ueskVA jPXfxZaNq23VuDcB6iBFXnK3e34llgo= X-Google-Smtp-Source: AK7set9LmuZsf96RMiFQcTbFuKJsiHKPQYuHCeUCI9ii3Tptg5r24rognBVcU5X5BJclqy7dfdtcUA== X-Received: by 2002:a17:906:2f0c:b0:878:61d8:d7c2 with SMTP id v12-20020a1709062f0c00b0087861d8d7c2mr4572956eji.39.1677930060991; Sat, 04 Mar 2023 03:41:00 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Aleksandar Rikalo , Artyom Tarasenko , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Paul Burton , Huacai Chen , BALATON Zoltan , Jiaxun Yang , "Michael S. Tsirkin" , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH 4/5] hw/pci/pci: Remove multifunction parameter from pci_create_simple_multifunction() Date: Sat, 4 Mar 2023 12:40:42 +0100 Message-Id: <20230304114043.121024-5-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304114043.121024-1-shentey@gmail.com> References: <20230304114043.121024-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=shentey@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677930110813100002 Content-Type: text/plain; charset="utf-8" There is also pci_create_simple() which creates non-multifunction PCI devices. Accordingly the parameter is always set to true when a multi function PCI device is to be created. The reason for the parameter's existence seems to be that it is used in the internal PCI code as well which is the only location where it gets set to false. This one usage can be replaced by trivial code. Remove this redundant, error-prone parameter. Signed-off-by: Bernhard Beschow --- include/hw/pci/pci.h | 1 - hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 4 ++-- hw/mips/boston.c | 3 +-- hw/mips/malta.c | 2 +- hw/pci/pci.c | 7 ++++--- 6 files changed, 9 insertions(+), 10 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index d5a40cd058..830407a5b9 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -578,7 +578,6 @@ PCIDevice *pci_new(int devfn, const char *name); bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); =20 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, - bool multifunction, const char *name); PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name); =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 2f16011bab..0cd430ccc5 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -235,7 +235,7 @@ static void pc_init1(MachineState *machine, : pc_pci_slot_get_pirq); pcms->bus =3D pci_bus; =20 - pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, typ= e); + pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, type); piix3 =3D PIIX3_PCI_DEVICE(pci_dev); piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 797ba347fd..65a862b66d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -299,7 +299,7 @@ static void pc_q35_init(MachineState *machine) ahci =3D pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SATA1_DEV, ICH9_SATA1_FUNC), - true, "ich9-ahci"); + "ich9-ahci"); idebus[0] =3D qdev_get_child_bus(&ahci->qdev, "ide.0"); idebus[1] =3D qdev_get_child_bus(&ahci->qdev, "ide.1"); g_assert(MAX_SATA_PORTS =3D=3D ahci_get_num_ports(ahci)); @@ -321,7 +321,7 @@ static void pc_q35_init(MachineState *machine) smb =3D pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC), - true, TYPE_ICH9_SMB_DEVICE); + TYPE_ICH9_SMB_DEVICE); pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(smb), "i2c")); =20 smbus_eeprom_init(pcms->smbus, 8, NULL, 0); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index a9d87f3437..2539606549 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -770,8 +770,7 @@ static void boston_mach_init(MachineState *machine) boston_lcd_event, NULL, s, NULL, true); =20 ahci =3D pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->se= c_bus, - PCI_DEVFN(0, 0), - true, TYPE_ICH9_AHCI); + PCI_DEVFN(0, 0), TYPE_ICH9_AHCI= ); g_assert(ARRAY_SIZE(hd) =3D=3D ahci_get_num_ports(ahci)); ide_drive_get(hd, ahci_get_num_ports(ahci)); ahci_ide_create_devs(ahci, hd); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ec172b111a..d4c79d263d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1254,7 +1254,7 @@ void mips_malta_init(MachineState *machine) pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq); =20 /* Southbridge */ - piix4 =3D pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, tr= ue, + piix4 =3D pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE); isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); =20 diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 034fe49e9a..c2e14f000e 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2111,17 +2111,18 @@ bool pci_realize_and_unref(PCIDevice *dev, PCIBus *= bus, Error **errp) } =20 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, - bool multifunction, const char *name) { - PCIDevice *dev =3D pci_new_multifunction(devfn, multifunction, name); + PCIDevice *dev =3D pci_new_multifunction(devfn, true, name); pci_realize_and_unref(dev, bus, &error_fatal); return dev; } =20 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) { - return pci_create_simple_multifunction(bus, devfn, false, name); + PCIDevice *dev =3D pci_new(devfn, name); + pci_realize_and_unref(dev, bus, &error_fatal); + return dev; } =20 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) --=20 2.39.2 From nobody Mon May 6 14:13:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1677930151; cv=none; d=zohomail.com; s=zohoarc; b=bev8/Zlh4Nzg35onJrCHk12hXqFAzyHsQ9NaNys+b6l9RRdKf2ffaZFqz1U9v38mHmK7UB7sEoPJw6CtFPruLVvXW71kFEML4ynA2h2RbuGsnBo3jRcyhxE0zsw2K9FYBZ7bGJyIsZnR4Yfohuf42dJKtsibeT1lZ4BCyxmS2gQ= ARC-Message-Signature: i=1; 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Tsirkin" , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Eduardo Habkost , qemu-ppc@nongnu.org, Richard Henderson , Paolo Bonzini , Bernhard Beschow Subject: [PATCH 5/5] hw/pci/pci: Remove multifunction parameter from pci_new_multifunction() Date: Sat, 4 Mar 2023 12:40:43 +0100 Message-Id: <20230304114043.121024-6-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304114043.121024-1-shentey@gmail.com> References: <20230304114043.121024-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=shentey@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677930153039100011 Content-Type: text/plain; charset="utf-8" There is also pci_new() which creates non-multifunction PCI devices. Accordingly the parameter is always set to true when a multi function PCI device is to be created. The reason for the parameter's existence seems to be that it is used in the internal PCI code as well which is the only location where it gets set to false. This one usage can be resolved by factoring out an internal helper function. Remove this redundant, error-prone parameter. Signed-off-by: Bernhard Beschow --- include/hw/pci/pci.h | 3 +-- hw/i386/pc_q35.c | 6 +++--- hw/mips/fuloong2e.c | 2 +- hw/pci-host/sabre.c | 6 ++---- hw/pci/pci.c | 13 +++++++++---- hw/ppc/pegasos2.c | 3 +-- hw/sparc64/sun4u.c | 5 ++--- 7 files changed, 19 insertions(+), 19 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 830407a5b9..cbf3ebea4e 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -572,8 +572,7 @@ pci_set_quad_by_mask(uint8_t *config, uint64_t mask, ui= nt64_t reg) pci_set_quad(config, (~mask & val) | (mask & rval)); } =20 -PCIDevice *pci_new_multifunction(int devfn, bool multifunction, - const char *name); +PCIDevice *pci_new_multifunction(int devfn, const char *name); PCIDevice *pci_new(int devfn, const char *name); bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp); =20 diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 65a862b66d..b41fc2b879 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -99,12 +99,12 @@ static int ehci_create_ich9_with_companions(PCIBus *bus= , int slot) return -1; } =20 - ehci =3D pci_new_multifunction(PCI_DEVFN(slot, 7), true, name); + ehci =3D pci_new_multifunction(PCI_DEVFN(slot, 7), name); pci_realize_and_unref(ehci, bus, &error_fatal); usbbus =3D QLIST_FIRST(&ehci->qdev.child_bus); =20 for (i =3D 0; i < 3; i++) { - uhci =3D pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true, + uhci =3D pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), comp[i].name); qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); @@ -236,7 +236,7 @@ static void pc_q35_init(MachineState *machine) phb =3D PCI_HOST_BRIDGE(q35_host); host_bus =3D phb->bus; /* create ISA bus */ - lpc =3D pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), = true, + lpc =3D pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), TYPE_ICH9_LPC_DEVICE); qdev_prop_set_bit(DEVICE(lpc), "smm-enabled", x86_machine_is_smm_enabled(x86ms)); diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 30944f8fe7..0d4a45bd4f 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -295,7 +295,7 @@ static void mips_fuloong2e_init(MachineState *machine) pci_bus =3D bonito_init((qemu_irq *)&(env->irq[2])); =20 /* South bridge -> IP5 */ - pci_dev =3D pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0), tr= ue, + pci_dev =3D pci_new_multifunction(PCI_DEVFN(FULOONG2E_VIA_SLOT, 0), TYPE_VT82C686B_ISA); qdev_connect_gpio_out(DEVICE(pci_dev), 0, env->irq[5]); pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index 949ecc21f2..dcb2e230b6 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -387,14 +387,12 @@ static void sabre_realize(DeviceState *dev, Error **e= rrp) pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); =20 /* APB secondary busses */ - pci_dev =3D pci_new_multifunction(PCI_DEVFN(1, 0), true, - TYPE_SIMBA_PCI_BRIDGE); + pci_dev =3D pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_SIMBA_PCI_BRID= GE); s->bridgeB =3D PCI_BRIDGE(pci_dev); pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); pci_realize_and_unref(pci_dev, phb->bus, &error_fatal); =20 - pci_dev =3D pci_new_multifunction(PCI_DEVFN(1, 1), true, - TYPE_SIMBA_PCI_BRIDGE); + pci_dev =3D pci_new_multifunction(PCI_DEVFN(1, 1), TYPE_SIMBA_PCI_BRID= GE); s->bridgeA =3D PCI_BRIDGE(pci_dev); pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); pci_realize_and_unref(pci_dev, phb->bus, &error_fatal); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c2e14f000e..09907c966e 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2089,8 +2089,8 @@ static void pci_qdev_realize(DeviceState *qdev, Error= **errp) pci_dev->msi_trigger =3D pci_msi_trigger; } =20 -PCIDevice *pci_new_multifunction(int devfn, bool multifunction, - const char *name) +static PCIDevice *pci_new_internal(int devfn, bool multifunction, + const char *name) { DeviceState *dev; =20 @@ -2100,9 +2100,14 @@ PCIDevice *pci_new_multifunction(int devfn, bool mul= tifunction, return PCI_DEVICE(dev); } =20 +PCIDevice *pci_new_multifunction(int devfn, const char *name) +{ + return pci_new_internal(devfn, true, name); +} + PCIDevice *pci_new(int devfn, const char *name) { - return pci_new_multifunction(devfn, false, name); + return pci_new_internal(devfn, false, name); } =20 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp) @@ -2113,7 +2118,7 @@ bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bu= s, Error **errp) PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, const char *name) { - PCIDevice *dev =3D pci_new_multifunction(devfn, true, name); + PCIDevice *dev =3D pci_new_multifunction(devfn, name); pci_realize_and_unref(dev, bus, &error_fatal); return dev; } diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index b0ada9c963..b8c8a60804 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -159,8 +159,7 @@ static void pegasos2_init(MachineState *machine) pci_bus =3D mv64361_get_pci_bus(pm->mv, 1); =20 /* VIA VT8231 South Bridge (multifunction PCI device) */ - via =3D OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), true, - TYPE_VT8231_ISA)); + via =3D OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), TYPE_VT8231_ISA= )); qdev_connect_gpio_out(DEVICE(via), 0, qdev_get_gpio_in_named(pm->mv, "gpp", 31)); pci_realize_and_unref(PCI_DEVICE(via), pci_bus, &error_fatal); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index a25e951f9d..b5d5a82c50 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -612,7 +612,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, pci_busA->slot_reserved_mask =3D 0xfffffff1; pci_busB->slot_reserved_mask =3D 0xfffffff0; =20 - ebus =3D pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS); + ebus =3D pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS); qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", hwdef->console_serial_base); pci_realize_and_unref(ebus, pci_busA, &error_fatal); @@ -648,8 +648,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, =20 if (!nd->model || strcmp(nd->model, "sunhme") =3D=3D 0) { if (!onboard_nic) { - pci_dev =3D pci_new_multifunction(PCI_DEVFN(1, 1), - true, "sunhme"); + pci_dev =3D pci_new_multifunction(PCI_DEVFN(1, 1), "sunhme= "); bus =3D pci_busA; memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); onboard_nic =3D true; --=20 2.39.2