From nobody Thu May 2 20:34:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677863393226527.3889871636957; Fri, 3 Mar 2023 09:09:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pY8tr-00063p-9L; Fri, 03 Mar 2023 12:08:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pY85A-0007se-Ms; Fri, 03 Mar 2023 11:16:32 -0500 Received: from azure-sdnproxy.icoremail.net ([20.231.56.155]) by eggs.gnu.org with smtp (Exim 4.90_1) (envelope-from ) id 1pY856-0008Tg-5l; Fri, 03 Mar 2023 11:16:32 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwAXlaasHQJkocIdAQ--.45954S2; Sat, 04 Mar 2023 00:17:48 +0800 (CST) Received: from localhost (unknown [113.247.214.165]) by mail (Coremail) with SMTP id AQAAfwCHYPArHQJkrYAAAA--.526S2; Sat, 04 Mar 2023 00:15:44 +0800 (CST) From: Chen Baozi To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH 1/2] target/arm: Add Neoverse-N1 registers Date: Sat, 4 Mar 2023 00:15:17 +0800 Message-Id: <20230303161518.3411149-2-chenbaozi@phytium.com.cn> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230303161518.3411149-1-chenbaozi@phytium.com.cn> References: <20230303161518.3411149-1-chenbaozi@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwCHYPArHQJkrYAAAA--.526S2 X-CM-SenderInfo: hfkh0updr2xqxsk13x1xpou0fpof0/1tbiAQAHEWQA7A0IoQAKsx Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=chenbaozi@ phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxWF17uF4UKw47Gry8WF1kGrg_yoW7Gr1kpF 1DJr15WF12qFsxXay8A34UCa95A3WFgr4jkrZFgryfuanxXrW5Kryqq34YgF98Ga4kJ34Y 9a1jq34Y9w17ZrUanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=20.231.56.155; envelope-from=chenbaozi@phytium.com.cn; helo=azure-sdnproxy.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 03 Mar 2023 12:08:53 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1677863394682100003 Content-Type: text/plain; charset="utf-8" Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Signed-off-by: Chen Baozi Tested-by: Marcin Juszkiewicz --- target/arm/cpu64.c | 2 ++ target/arm/cpu_tcg.c | 62 ++++++++++++++++++++++++++++++++++++++++++ target/arm/internals.h | 2 ++ 3 files changed, 66 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da1..a6ae7cafac 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1094,6 +1094,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj) =20 /* From D5.1 AArch64 PMU register summary */ cpu->isar.reset_pmcr_el0 =3D 0x410c3000; + + define_neoverse_n1_cp_reginfo(cpu); } =20 static void aarch64_host_initfn(Object *obj) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index df0c45e523..6a1bb56b25 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -150,6 +150,68 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } + +static const ARMCPRegInfo neoverse_n1_cp_reginfo[] =3D { + { .name =3D "ATCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ATCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ATCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ATCR_EL12", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 15, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "AVTCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 15, .crm =3D 7, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR3_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUCFR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 1, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0x961563= 010 }, + { .name =3D "CPUPCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPMR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 3, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPOR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 2, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPSELR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 8, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUPWRCTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ERXPFGCDN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ERXPFGCTL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ERXPFGF_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, +}; + +void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); +} #endif /* !CONFIG_USER_ONLY */ =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 3c7341e774..0c393e971a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1356,8 +1356,10 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp= ); =20 #ifdef CONFIG_USER_ONLY static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } +static inline void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) {} #else void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); +void define_neoverse_n1_cp_reginfo(ARMCPU *cpu); #endif =20 bool el_is_in_host(CPUARMState *env, int el); --=20 2.37.3 From nobody Thu May 2 20:34:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677863352203340.67733186056466; Fri, 3 Mar 2023 09:09:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pY8ts-000647-03; Fri, 03 Mar 2023 12:08:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pY84p-0007RA-UW; Fri, 03 Mar 2023 11:16:12 -0500 Received: from azure-sdnproxy.icoremail.net ([20.232.28.96]) by eggs.gnu.org with smtp (Exim 4.90_1) (envelope-from ) id 1pY84i-0008VH-VF; Fri, 03 Mar 2023 11:16:11 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwBHEJUaHQJkBzv_BQ--.41741S2; Sat, 04 Mar 2023 00:15:22 +0800 (CST) Received: from localhost (unknown [113.247.214.165]) by mail (Coremail) with SMTP id AQAAfwCHZPQ7HQJks4AAAA--.564S2; Sat, 04 Mar 2023 00:16:01 +0800 (CST) From: Chen Baozi To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH 2/2] target/arm: Add DynamIQ Shared Unit control registers Date: Sat, 4 Mar 2023 00:15:18 +0800 Message-Id: <20230303161518.3411149-3-chenbaozi@phytium.com.cn> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230303161518.3411149-1-chenbaozi@phytium.com.cn> References: <20230303161518.3411149-1-chenbaozi@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwCHZPQ7HQJks4AAAA--.564S2 X-CM-SenderInfo: hfkh0updr2xqxsk13x1xpou0fpof0/1tbiAQAHEWQA7A0IoQALsw Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=chenbaozi@ phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxAr4Uur45Gr48tr4ktFyrJFb_yoWrJw45pF nrJry5WFy2qFsxJF4xCw12kaykAa4F9rWjkrsFgr9a9F4aq3y5KFyqqa45Kr98Ka1kA34j ka1jqryj9w47ZrUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=20.232.28.96; envelope-from=chenbaozi@phytium.com.cn; helo=azure-sdnproxy.icoremail.net X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 03 Mar 2023 12:08:53 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1677863354098100003 Content-Type: text/plain; charset="utf-8" DynamIQ Shared Unit (DSU) contains system control registers in the SCU and L3 logic which are implemented as the system registers for the cores in the cluster. Add DSU control registers and enable it to the supported cores. Signed-off-by: Chen Baozi --- target/arm/cpu_tcg.c | 52 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 6a1bb56b25..db6163ede2 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -208,9 +208,61 @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] =3D= { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 +static const ARMCPRegInfo dsu_cp_reginfo[] =3D { + { .name =3D "CLUSTERCFR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERIDR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERREVIDR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERPWRCTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 5, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERPWRDN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERPWRSTAT_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 3, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERTHREADSID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERACPSID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERSTASHSID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERPARTCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERBUSQOS_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERL3HIT_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 5, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERL3MISS_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CLUSTERTHREADSIDOVR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 15, .crm =3D 4, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, +}; + void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) { define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); + define_arm_cp_regs(cpu, dsu_cp_reginfo); } #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.37.3