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charset="utf-8" Content-Transfer-Encoding: quoted-printable Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Daniel Henrique Barboza , Weiwei Li , ilippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=palmer@rivosinc.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1677833306125100019 From: Daniel Henrique Barboza This file has several uses of env_archcpu() that are used solely to read cfg->vlen. Use the new riscv_cpu_cfg() inline instead. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Weiwei Li Message-ID: <20230226170514.588071-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/vector_helper.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7e476ea8c3..2423affe37 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -272,7 +272,7 @@ static void vext_set_tail_elems_1s(CPURISCVState *env, = target_ulong vl, uint32_t esz, uint32_t max_elems) { uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; uint32_t vta =3D vext_vta(desc); uint32_t registers_used; int k; @@ -671,7 +671,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVSt= ate *env, uint32_t desc, { uint32_t i, k, off, pos; uint32_t nf =3D vext_nf(desc); - uint32_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint32_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; uint32_t max_elems =3D vlenb >> log2_esz; =20 k =3D env->vstart / max_elems; @@ -1141,7 +1141,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vl =3D env->vl; \ uint32_t vm =3D vext_vm(desc); \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ @@ -1177,7 +1177,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , \ { \ uint32_t vl =3D env->vl; \ uint32_t vm =3D vext_vm(desc); \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ \ @@ -1376,7 +1376,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -1439,7 +1439,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -4152,7 +4152,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -4190,7 +4190,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, vo= id *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ @@ -4721,7 +4721,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; \ + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; \ uint32_t vta_all_1s =3D vext_vta_all_1s(desc); \ uint32_t i; \ int a, b; \ @@ -4808,7 +4808,7 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPU= RISCVState *env, { uint32_t vm =3D vext_vm(desc); uint32_t vl =3D env->vl; - uint32_t total_elems =3D env_archcpu(env)->cfg.vlen; + uint32_t total_elems =3D riscv_cpu_cfg(env)->vlen; uint32_t vta_all_1s =3D vext_vta_all_1s(desc); uint32_t vma =3D vext_vma(desc); int i; --=20 2.39.2