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d=1e100.net; s=20210112; t=1677832926; h=to:from:cc:content-transfer-encoding:mime-version:references :in-reply-to:message-id:date:subject:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PBboFqD/kSBEIR1p31nwYTGVAdZxVLQHofC0o83aLNg=; b=gWSmNIhjV6+AoKPmMSfM4+0J6zW/SiVUR8hYpPntiwS8v1kwrZAxyl06fU976LvPKV OPHB3Szs30khyWAXsqSAAci1R6ifagHjJWPA/87YduD0jbI4Wc9C92YEfNGyn9zT/vLb 3HkxMc49tdB8e2CkenJORBUj1C9ON+SfPxGVKOb+XP14Ji0BUlNFp3IOEwXgzMJmCipr juPUGHfQ9jcmqfVdpxkqeyg4ZZdZzypxtAHTkJrGelfFMF9zQITNLbG2+mSId/EM7H4i J6Rh5B5BnAJbQCCv0i5pRcs7ELypd5hkebmHKeRAsiGmNYGFCBZEXMmpz7POvMkUG+8C yX8g== X-Gm-Message-State: AO0yUKWO77yGnn8ae9i5h3xsgMHqNGcXN2PZJ+ZM3/hEObWpBhIvSY2x MUaxjPx93mRTn4oD96QoqfDUzA== X-Google-Smtp-Source: AK7set9yXCtCADC3lfxxEYaKAIqkY9b2OqkFxn1Sfy8dtJDJwjsTrwJbnvSaKYOgR4pJHBjtNliuiw== X-Received: by 2002:a17:903:187:b0:19e:6d83:8277 with SMTP id z7-20020a170903018700b0019e6d838277mr1516563plg.51.1677832925945; Fri, 03 Mar 2023 00:42:05 -0800 (PST) Subject: [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Date: Fri, 3 Mar 2023 00:37:17 -0800 Message-Id: <20230303083740.12817-37-palmer@rivosinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230303083740.12817-1-palmer@rivosinc.com> References: <20230303083740.12817-1-palmer@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng , Weiwei Li , LIU Zhiwei , Palmer Dabbelt From: Palmer Dabbelt To: Peter Maydell Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=palmer@rivosinc.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1677833304158100012 Content-Type: text/plain; charset="utf-8" From: Bin Meng It's worth noting that the vector CSR predicate() has a similar run-time check logic to the FPU CSR. With the previous patch our gdbstub can correctly report these vector CSRs via the CSR xml. Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 = & rv32") inserted these vector CSRs in an ad-hoc, non-standard way in the riscv-vector.xml. Now we can treat these CSRs no different from other CSRs. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230228104035.1879882-13-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 75 ------------------------------------------ 1 file changed, 75 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ef52f41460..6048541606 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -127,40 +127,6 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8= _t *mem_buf, int n) return 0; } =20 -/* - * Convert register index number passed by GDB to the correspond - * vector CSR number. Vector CSRs are defined after vector registers - * in dynamic generated riscv-vector.xml, thus the starting register index - * of vector CSRs is 32. - * Return 0 if register index number is out of range. - */ -static int riscv_gdb_vector_csrno(int num_regs) -{ - /* - * The order of vector CSRs in the switch case - * should match with the order defined in csr_ops[]. - */ - switch (num_regs) { - case 32: - return CSR_VSTART; - case 33: - return CSR_VXSAT; - case 34: - return CSR_VXRM; - case 35: - return CSR_VCSR; - case 36: - return CSR_VL; - case 37: - return CSR_VTYPE; - case 38: - return CSR_VLENB; - default: - /* Unknown register. */ - return 0; - } -} - static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) { uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; @@ -174,19 +140,6 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GB= yteArray *buf, int n) return cnt; } =20 - int csrno =3D riscv_gdb_vector_csrno(n); - - if (!csrno) { - return 0; - } - - target_ulong val =3D 0; - int result =3D riscv_csrrw_debug(env, csrno, &val, 0, 0); - - if (result =3D=3D RISCV_EXCP_NONE) { - return gdb_get_regl(buf, val); - } - return 0; } =20 @@ -201,19 +154,6 @@ static int riscv_gdb_set_vector(CPURISCVState *env, ui= nt8_t *mem_buf, int n) return vlenb; } =20 - int csrno =3D riscv_gdb_vector_csrno(n); - - if (!csrno) { - return 0; - } - - target_ulong val =3D ldtul_p(mem_buf); - int result =3D riscv_csrrw_debug(env, csrno, NULL, val, -1); - - if (result =3D=3D RISCV_EXCP_NONE) { - return sizeof(target_ulong); - } - return 0; } =20 @@ -361,21 +301,6 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, = int base_reg) num_regs++; } =20 - /* Define vector CSRs */ - const char *vector_csrs[7] =3D { - "vstart", "vxsat", "vxrm", "vcsr", - "vl", "vtype", "vlenb" - }; - - for (i =3D 0; i < 7; i++) { - g_string_append_printf(s, - "", - vector_csrs[i], TARGET_LONG_BITS, base_reg+= +); - num_regs++; - } - g_string_append_printf(s, ""); =20 cpu->dyn_vreg_xml =3D g_string_free(s, false); --=20 2.39.2