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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=123.126.96.234; envelope-from=qianfanguijin@163.com; helo=m12.mail.163.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @163.com) X-ZM-MESSAGEID: 1677757436302100006 Content-Type: text/plain; charset="utf-8" From: qianfan Zhao Next is an example when read/write trace enabled: allwinner_i2c_write write XADDR(0x04): 0x00 allwinner_i2c_write write CNTR(0x0c): 0x50 M_STP BUS_EN allwinner_i2c_write write CNTR(0x0c): 0xe4 A_ACK M_STA BUS_EN INT_EN allwinner_i2c_read read CNTR(0x0c): 0xcc A_ACK INT_FLAG BUS_EN INT_EN allwinner_i2c_read read STAT(0x10): 0x08 STAT_M_STA_TX Signed-off-by: qianfan Zhao --- hw/i2c/allwinner-i2c.c | 110 ++++++++++++++++++++++++++++++++++++++++- hw/i2c/trace-events | 5 +- 2 files changed, 110 insertions(+), 5 deletions(-) diff --git a/hw/i2c/allwinner-i2c.c b/hw/i2c/allwinner-i2c.c index a435965836..fa650e7e02 100644 --- a/hw/i2c/allwinner-i2c.c +++ b/hw/i2c/allwinner-i2c.c @@ -129,6 +129,39 @@ enum { STAT_IDLE =3D 0x1f } TWI_STAT_STA; =20 +#define TWI_STAT_STA_DESC(sta) [sta] =3D #sta +static const char *twi_stat_sta_descriptors[] =3D { + TWI_STAT_STA_DESC(STAT_BUS_ERROR), + TWI_STAT_STA_DESC(STAT_M_STA_TX), + TWI_STAT_STA_DESC(STAT_M_RSTA_TX), + TWI_STAT_STA_DESC(STAT_M_ADDR_WR_ACK), + TWI_STAT_STA_DESC(STAT_M_ADDR_WR_NACK), + TWI_STAT_STA_DESC(STAT_M_DATA_TX_ACK), + TWI_STAT_STA_DESC(STAT_M_DATA_TX_NACK), + TWI_STAT_STA_DESC(STAT_M_ARB_LOST), + TWI_STAT_STA_DESC(STAT_M_ADDR_RD_ACK), + TWI_STAT_STA_DESC(STAT_M_ADDR_RD_NACK), + TWI_STAT_STA_DESC(STAT_M_DATA_RX_ACK), + TWI_STAT_STA_DESC(STAT_M_DATA_RX_NACK), + TWI_STAT_STA_DESC(STAT_S_ADDR_WR_ACK), + TWI_STAT_STA_DESC(STAT_S_ARB_LOST_AW_ACK), + TWI_STAT_STA_DESC(STAT_S_GCA_ACK), + TWI_STAT_STA_DESC(STAT_S_ARB_LOST_GCA_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_SA_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_SA_NACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_GCA_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_RX_GCA_NACK), + TWI_STAT_STA_DESC(STAT_S_STP_RSTA), + TWI_STAT_STA_DESC(STAT_S_ADDR_RD_ACK), + TWI_STAT_STA_DESC(STAT_S_ARB_LOST_AR_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_TX_ACK), + TWI_STAT_STA_DESC(STAT_S_DATA_TX_NACK), + TWI_STAT_STA_DESC(STAT_S_LB_TX_ACK), + TWI_STAT_STA_DESC(STAT_M_2ND_ADDR_WR_ACK), + TWI_STAT_STA_DESC(STAT_M_2ND_ADDR_WR_NACK), + TWI_STAT_STA_DESC(STAT_IDLE), +}; + static const char *allwinner_i2c_get_regname(unsigned offset) { switch (offset) { @@ -155,6 +188,79 @@ static const char *allwinner_i2c_get_regname(unsigned = offset) } } =20 +static const char *twi_cntr_reg_bits[] =3D { + [2] =3D "A_ACK", + [3] =3D "INT_FLAG", + [4] =3D "M_STP", + [5] =3D "M_STA", + [6] =3D "BUS_EN", + [7] =3D "INT_EN", +}; + +static const char *twi_line_ctrl_reg_bits[] =3D { + [5] =3D "SCL_STATE", + [4] =3D "SDA_STATE", + [3] =3D "SCL_CTL", + [2] =3D "SCL_CTL_EN", + [1] =3D "SDA_CTL", + [0] =3D "SDA_CTL_EN", +}; + +static void make_reg_value_bit_descriptors(char *s, size_t sz, uint8_t val= ue, + const char **desc_arrays, + size_t array_size) +{ + unsigned i =3D 0; + + for (; i < array_size; i++) { + if ((value & (1 << i)) && desc_arrays[i]) { + strncat(s, desc_arrays[i], sz - 1); + strncat(s, " ", sz - 1); + } + } +} + +static void make_reg_value_descriptors(char *s, size_t sz, uint8_t addr, + uint8_t value) +{ + switch (addr) { + case TWI_CNTR_REG: + make_reg_value_bit_descriptors(s, sz, value, twi_cntr_reg_bits, + ARRAY_SIZE(twi_cntr_reg_bits)); + break; + case TWI_LCR_REG: + make_reg_value_bit_descriptors(s, sz, value, twi_line_ctrl_reg_bit= s, + ARRAY_SIZE(twi_line_ctrl_reg_bits)); + break; + case TWI_STAT_REG: + if (STAT_TO_STA(value) <=3D STAT_IDLE) + strncat(s, twi_stat_sta_descriptors[STAT_TO_STA(value)], sz - = 1); + break; + } +} + +static void allwinner_i2c_trace_read(uint8_t addr, uint8_t value) +{ + char desc[256] =3D { 0 }; + + if (trace_event_get_state_backends(TRACE_ALLWINNER_I2C_READ)) { + make_reg_value_descriptors(desc, sizeof(desc), addr, value); + trace_allwinner_i2c_read(allwinner_i2c_get_regname(addr), + addr, value, desc); + } +} + +static void allwinner_i2c_trace_write(uint8_t addr, uint8_t value) +{ + char desc[256] =3D { 0 }; + + if (trace_event_get_state_backends(TRACE_ALLWINNER_I2C_WRITE)) { + make_reg_value_descriptors(desc, sizeof(desc), addr, value); + trace_allwinner_i2c_write(allwinner_i2c_get_regname(addr), + addr, value, desc); + } +} + static inline bool allwinner_i2c_is_reset(AWI2CState *s) { return s->srst & TWI_SRST_MASK; @@ -271,7 +377,7 @@ static uint64_t allwinner_i2c_read(void *opaque, hwaddr= offset, break; } =20 - trace_allwinner_i2c_read(allwinner_i2c_get_regname(offset), offset, va= lue); + allwinner_i2c_trace_read((uint8_t)offset, (uint8_t)value); =20 return (uint64_t)value; } @@ -283,7 +389,7 @@ static void allwinner_i2c_write(void *opaque, hwaddr of= fset, =20 value &=3D 0xff; =20 - trace_allwinner_i2c_write(allwinner_i2c_get_regname(offset), offset, v= alue); + allwinner_i2c_trace_write((uint8_t)offset, (uint8_t)value); =20 switch (offset) { case TWI_ADDR_REG: diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events index 8e88aa24c1..963946bfdb 100644 --- a/hw/i2c/trace-events +++ b/hw/i2c/trace-events @@ -16,9 +16,8 @@ i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x= ) data:0x%02x" i2c_ack(void) "" =20 # allwinner_i2c.c - -allwinner_i2c_read(const char* reg_name, uint64_t offset, uint64_t value) = "read %s [0x%" PRIx64 "]: -> 0x%" PRIx64 -allwinner_i2c_write(const char* reg_name, uint64_t offset, uint64_t value)= "write %s [0x%" PRIx64 "]: <- 0x%" PRIx64 +allwinner_i2c_read(const char *regname, uint8_t addr, uint8_t value, const= char *desc) " read %6s(0x%02x): 0x%02x %s" +allwinner_i2c_write(const char *regname, uint8_t addr, uint8_t value, cons= t char *desc) "write %6s(0x%02x): 0x%02x %s" =20 # aspeed_i2c.c =20 --=20 2.25.1