From nobody Sun Feb 8 21:28:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1677497477; cv=none; d=zohomail.com; s=zohoarc; b=PmHDVK9YA19XBsJUkAQeCEjxsvB3L4OBp5GD6v18HpgJkmIVtSkPWKxEgF9hbzC5wB0zRke7q1SHYg/6nw9iuJv9amij5ohJthHhy1QvJVTaubd4cfTZ9b0YOTRK3sowMMOIO4jILaYgsRXK3Qg68gdKg5XdWRhtJkQ7CQxNg6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677497477; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QW1bB72lBygMaF4FL3iHPoILVNOF4ZMBuvxduS7xZKY=; b=DXEKfANjiMocrH0nka5RPhg2q08VYM/dqPe+U5BTQrzEMR9lVvEiED752tlOKCNzI54Q0ZqD/oRQYGvMNOKMTMKqNjl99jFOsWN/nN3Q7sHbYrzFbb1NBEIMwwJn/cpRiSBvtgrgCmF+XIYLK+3wQz6ZNQrXmRXaesneMj6qMJ8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677497477309182.47004182023568; Mon, 27 Feb 2023 03:31:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWbij-0008H4-Ui; Mon, 27 Feb 2023 06:31:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWbib-0007xj-Pj for qemu-devel@nongnu.org; Mon, 27 Feb 2023 06:31:02 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWbia-0004Sz-1F for qemu-devel@nongnu.org; Mon, 27 Feb 2023 06:30:57 -0500 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.201]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PQJCn1ZKWz6J9fR; Mon, 27 Feb 2023 19:28:37 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 27 Feb 2023 11:30:53 +0000 To: , Michael Tsirkin CC: Ben Widawsky , , , Ira Weiny , Gregory Price , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mike Maslenkin , Dave Jiang , Markus Armbruster , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Thomas Huth Subject: [PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Date: Mon, 27 Feb 2023 11:27:49 +0000 Message-ID: <20230227112751.6101-7-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230227112751.6101-1-Jonathan.Cameron@huawei.com> References: <20230227112751.6101-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500002.china.huawei.com (7.191.160.78) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1677497477557100001 As these are about to be modified, fix the endian handle for this set of registers rather than making it worse. Note that CXL is currently only supported in QEMU on x86 (arm64 patches out of tree) so we aren't going to yet hit an problems with big endian. However it is good to avoid making things worse for that support in the future. Reviewed-by: Dave Jiang Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-component-utils.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 3edd303a33..737b4764b9 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -141,17 +141,17 @@ static void ras_init_common(uint32_t *reg_state, uint= 32_t *write_msk) * Error status is RW1C but given bits are not yet set, it can * be handled as RO. */ - reg_state[R_CXL_RAS_UNC_ERR_STATUS] =3D 0; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0); /* Bits 12-13 and 17-31 reserved in CXL 2.0 */ - reg_state[R_CXL_RAS_UNC_ERR_MASK] =3D 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_MASK] =3D 0x1cfff; - reg_state[R_CXL_RAS_UNC_ERR_SEVERITY] =3D 0x1cfff; - write_msk[R_CXL_RAS_UNC_ERR_SEVERITY] =3D 0x1cfff; - reg_state[R_CXL_RAS_COR_ERR_STATUS] =3D 0; - reg_state[R_CXL_RAS_COR_ERR_MASK] =3D 0x7f; - write_msk[R_CXL_RAS_COR_ERR_MASK] =3D 0x7f; + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0); + stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f); + stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f); /* CXL switches and devices must set */ - reg_state[R_CXL_RAS_ERR_CAP_CTRL] =3D 0x00; + stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x00); } =20 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, --=20 2.37.2