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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id j10-20020a170902690a00b001992e74d058sm2665348plk.7.2023.02.20.15.26.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 15:26:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kl7nsc9p6BIDSk+FSIUoP/kFXINcnp5gsZ8dnkbWdwU=; b=Px0cV/J3cA5nxUSIyPH4WmDlrGXHRfWGHBHPLb9gDVPzqc5DzcQKJSyzqE9QlLI+KI MP0WilTKdLe3pXXIH00HYQMyLsx62Pkqwk6Y/a1VB8bKZpfoW7Bizazr8jZyFSj1hq6E ASiaiGbPrGXVTacms4f97QAVgpX0FOiK7uTEzf/O7O6hgzlAo4w3JO1TwflpHZIYew6h yICHGIc4nhDV/KSmGXZXjCaqbpkBKNmpArxqGPrBv4FQy+j/U1cr+O25W87Znir7OezD 6WLLXy02d05orj0R+erfCvNimihBA7U8BBPh4y3xIYrv5aXNr7uAJtTLWTEX1Ok7JS/i 1+uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kl7nsc9p6BIDSk+FSIUoP/kFXINcnp5gsZ8dnkbWdwU=; b=PC5wWMlxetl122Buf3Vbf72iPYj+p0/4b7bMnJ5s9q9mIXBwy1wexqAAasoSvc9LH6 gRe5Md8G+rAZAWO07lMd9fmLzVa07dc+PcqYx2ZnClBqs0F16lPsDHIIcmcXyHIErLwn xSSoO/RSgShkll1Lbr9FpQnJssGkEZsXYFtVrvmHzzkHObLZ39yo9oTe/w9IQ6759tkC B8wxozJiY2woENNmMX36Ne9JGYz+qDLYf5tqqZj0eRm5Ez3aMmKWoM+pOMWwWtu/T4l5 j4ZtQ15y1pPyILxgmEB7JTNnhMifMZOb8WeqoDd0/lVBWmWaKSN0ga/le7/DRmF13R4r EcGg== X-Gm-Message-State: AO0yUKX6UfbgJnXUpOzFlIA0CBpRMF75VtnTQu7lkqzAOlYCvQlzFdIw DvB8MuR7yS8bZ3iaYCuHV9t6IFramAcHU+EaUT4= X-Google-Smtp-Source: AK7set9oK+uPEm+3vH1QvaKLOxUIa34L6NNOmCGnpIXWHgpDNECQNLjTZp2y1S/wpJm7LV9tqytOWg== X-Received: by 2002:a17:902:d4cc:b0:19b:dc8:c67b with SMTP id o12-20020a170902d4cc00b0019b0dc8c67bmr2462597plg.50.1676935598836; Mon, 20 Feb 2023 15:26:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 05/21] target/arm: Add RME cpregs Date: Mon, 20 Feb 2023 13:26:10 -1000 Message-Id: <20230220232626.429947-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220232626.429947-1-richard.henderson@linaro.org> References: <20230220232626.429947-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676935726001100010 Content-Type: text/plain; charset="utf-8" This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 19 +++++++++++ target/arm/helper.c | 83 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 486baf3924..6a97c727d1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -541,6 +541,11 @@ typedef struct CPUArchState { uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ uint64_t fgt_exec[1]; /* HFGITR */ + + /* RME registers */ + uint64_t gpccr_el3; + uint64_t gptbr_el3; + uint64_t mfar_el3; } cp15; =20 struct { @@ -1043,6 +1048,7 @@ struct ArchCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + uint8_t reset_l0gptsz; =20 /* * Intermediate values used during property parsing. @@ -2336,6 +2342,19 @@ FIELD(MVFR1, SIMDFMAC, 28, 4) FIELD(MVFR2, SIMDMISC, 0, 4) FIELD(MVFR2, FPMISC, 4, 4) =20 +FIELD(GPCCR, PPS, 0, 3) +FIELD(GPCCR, IRGN, 8, 2) +FIELD(GPCCR, ORGN, 10, 2) +FIELD(GPCCR, SH, 12, 2) +FIELD(GPCCR, PGS, 14, 2) +FIELD(GPCCR, GPC, 16, 1) +FIELD(GPCCR, GPCP, 17, 1) +FIELD(GPCCR, L0GPTSZ, 20, 4) + +FIELD(MFAR, FPA, 12, 40) +FIELD(MFAR, NSE, 62, 1) +FIELD(MFAR, NS, 63, 1) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index 2ebca3e2b6..c769218763 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6932,6 +6932,83 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D access_esm, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; + +static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush(cs); +} + +static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* L0GPTSZ is RO; other bits not mentioned are RES0. */ + uint64_t rw_mask =3D R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | + R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | + R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; + + env->cp15.gpccr_el3 =3D (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw= _mask); +} + +static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + env->cp15.gpccr_el3 =3D FIELD_DP64(0, GPCCR, L0GPTSZ, + env_archcpu(env)->reset_l0gptsz); +} + +static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static const ARMCPRegInfo rme_reginfo[] =3D { + { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, + .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, + .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, + { .name =3D "MFAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 5, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mfar= _el3) }, + { .name =3D "TLBI_PAALL", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paall_write }, + { .name =3D "TLBI_PAALLOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + /* + * QEMU does not have a way to invalidate by physical address, thus + * invalidating a range of physical addresses is accomplished by + * flushing all tlb entries in the outer sharable domain, + * just like PAALLOS. + */ + { .name =3D "TLBI_RPALOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "TLBI_RPAOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "DC_CIPAPA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NOP }, +}; + +static const ARMCPRegInfo rme_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAPA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NOP }, +}; #endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9123,6 +9200,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbios, cpu)) { define_arm_cp_regs(cpu, tlbios_reginfo); } + if (cpu_isar_feature(aa64_rme, cpu)) { + define_arm_cp_regs(cpu, rme_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, rme_mte_reginfo); + } + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.34.1