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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id j10-20020a170902690a00b001992e74d058sm2665348plk.7.2023.02.20.15.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 15:26:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q2wDlc9y+ZmDdlYUvnbEL+qYl6ONKTEgAFqhyLih/rk=; b=SI9939CkfMXh2gPFkBNyfUSn311jdAXhlcxpI26CQBa3jmX48aYVUJnNUe298tv0tA /55rvZT1CahipYUH1Ds2W1emizOmKY1KMHEU2McyMcTk5Ao+cM0895YjzE0oVYAZyO9N gaQAUwBjTxhKcIBvHFgpNgWsr1lanhNcQWEz6QMY/nM8ywl9WNlJnL0Z+NoJC+M4rKw5 YlJkGHlgHVgr1LiYKywbBMqXEZpHmEO13E1a3u94o6N0MKb7RhgNEouS4cgr51/G+lhE c4x0uqPh03jiltHhtgLOENZ2EFiy6G/ANfowJLNf13Vo3+O3RfklFKG8YAJZfFVpg+Ao 0Q4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q2wDlc9y+ZmDdlYUvnbEL+qYl6ONKTEgAFqhyLih/rk=; b=YoqeTugKycJ9mJGjDnQ0btWiO8AhbOgFdf8Cht+yQ//rMk2CXlDixZP9EsBsibWeZb PcK0ho4sDhqy+8uHltztTST3HWvBFPqKveuKdUP6Y25F8Y0fjO7nPjxHCgKC3hpXUqRJ 2r+xiDHSbpUc1oryGi7gaBBM1kK+LiskJT7xEjjERhkhmsbFMd+MaAPb7op007BaIyzy 6ynyF7EegBJncjjFTeAKCW8ei5CFz4kHiZKWrUfru7b81vOSEIezuoQQ1z1Cp8Ys4NjU n9NK5nR63hFzX9B6SPrOK5UptnLohEC2WlL8DGg1EeiBERa1pABLHbnf/X/CzA9zoXb7 4VVw== X-Gm-Message-State: AO0yUKUi1XaG5dAveS1VT358/CNU3+EAC0domKdLnbKt610lbWfqNELb lt/a3VtkWl/UTp5AutgCe8TKkPahRELH4HZD6D0= X-Google-Smtp-Source: AK7set9o3MJdoyqvShsoANoAbvyvIKMD7GTRBRg6+0Flhz29P2jnqB33ViymxM1ZQZTDp7gXc+/bKw== X-Received: by 2002:a17:902:e547:b0:19a:a815:2876 with SMTP id n7-20020a170902e54700b0019aa8152876mr4075649plf.62.1676935610970; Mon, 20 Feb 2023 15:26:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 13/21] target/arm: Handle no-execute for Realm and Root regimes Date: Mon, 20 Feb 2023 13:26:18 -1000 Message-Id: <20230220232626.429947-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220232626.429947-1-richard.henderson@linaro.org> References: <20230220232626.429947-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676935762150100001 Content-Type: text/plain; charset="utf-8" While Root and Realm may read and write data from other spaces, neither may execute from other pa spaces. This happens for Stage1 EL3, EL2, EL2&0, but stage2 EL1&0. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 52 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a9a9a8a403..54e72baff5 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -909,7 +909,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +static int get_S2prot_noexecute(int s2ap) { int prot =3D 0; =20 @@ -919,6 +919,12 @@ static int get_S2prot(CPUARMState *env, int s2ap, int = xn, bool s1_is_el0) if (s2ap & 2) { prot |=3D PAGE_WRITE; } + return prot; +} + +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot =3D get_S2prot_noexecute(s2ap); =20 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -984,9 +990,39 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_= idx, bool is_aa64, } } =20 - if (out_pa =3D=3D ARMSS_NonSecure && in_pa =3D=3D ARMSS_Secure && - (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; + if (in_pa !=3D out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + return prot_rw; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + switch (mmu_idx) { + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + return prot_rw; + default: + break; + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + return prot_rw; + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } } =20 /* TODO have_wxn should be replaced with @@ -1563,12 +1599,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. + * R_YMCSL: Executing an insn fetched from non-Realm causes + * a stage2 permission fault. */ if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { out_space =3D ARMSS_NonSecure; + result->f.prot =3D get_S2prot_noexecute(ap); + } else { + xn =3D extract64(attrs, 53, 2); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } - xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { int nse, ns =3D extract32(attrs, 5, 1); switch (out_space) { --=20 2.34.1