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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id j10-20020a170902690a00b001992e74d058sm2665348plk.7.2023.02.20.15.26.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 15:26:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HSjxF6mCj3nhvrrRuM2gW/YQifDnxgBhjfPXSNiexPo=; b=Hn5CVnt26hi2yiCnvLgQOUl1+yYVFihNbd4J/h2R7kWNESobiiiz7tDXYm0kRljD1X mR5Kjref2/gmuTIbCASXlyl6wD+WDOq8qlOGBphAxe4be5Tq5yK9L0+C5jvWPgQXfukQ YrhMcq7u6Wp4FOqkW0U9KYJWvez9Ac0za6j9fGIGP7PscWw7KqsgqMPd7Ifn7nmpvVsY WWhmmzlHNcRik0YsMAo3EifHSKOMcPB5hA/3W7AZxqNJ2vxMjTf4McXjiEqmW+W8T/0R blBSUD6w6f1aZVaZpoUWNkYG2yusF4J6iecfYW8fggyjdVCKVuz4t6S2XrNY1t5BKOrB L5xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HSjxF6mCj3nhvrrRuM2gW/YQifDnxgBhjfPXSNiexPo=; b=Qb0ZjJi2upHhikJXcneal/fuSRQ123lrQpGgTrgwdtP+NgvR9u8LFs58hHBuwrcze4 VhU5o6x0PC1KDdTUFRsXcB22FwjCRw1c47duJWSROvA6X7YOiAg5s5+xFzfIky4jbc/x sGZTF4iK82zkyy+39BoXumKErcqXx1v5spGmrni3qFJTMT7QXuvdhl/Ip3yQIljktvIh AMvN9a0FANoKxrAe38s8kbTNVYh+dMoCtQS6ZRg04ZeUQbzRaqggYqC7i4hH2iyjgxP0 MPN9kEIc7DRC0ZGtlrxAV4RV8ry1WW24fq6g30Cm6H2nG/fQikJaMx+STVwTXm7X2dLf SxyA== X-Gm-Message-State: AO0yUKVqm3KJtl/7GwinOtg3R0o7eOYJ/Ek0lppWJiZaqt6yskqi79Mn tAnZzad7UDu3Q+xv6SzXguQsyOP0kG85P6zuQY0MuQ== X-Google-Smtp-Source: AK7set+is2YTRiTj+jTA+bocJJ2QWYyLGJ24N0TqNUyFdbiNHh6bQVGyT+iXebUDXe58065szIYzRw== X-Received: by 2002:a05:6a21:32a9:b0:bc:930e:4165 with SMTP id yt41-20020a056a2132a900b000bc930e4165mr3395695pzb.15.1676935606791; Mon, 20 Feb 2023 15:26:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 10/21] target/arm: Pipe ARMSecuritySpace through ptw.c Date: Mon, 20 Feb 2023 13:26:15 -1000 Message-Id: <20230220232626.429947-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230220232626.429947-1-richard.henderson@linaro.org> References: <20230220232626.429947-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676935685864100003 Content-Type: text/plain; charset="utf-8" Add input and output space members to S1Translate. Set and adjust them in S1_ptw_translate, and the various points at which we drop secure state. Initialize the space in get_phys_addr; for now leave get_phys_addr_with_secure considering only secure vs non-secure spaces. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 95 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 76 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5a0c5edc88..7745287a46 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -19,11 +19,13 @@ typedef struct S1Translate { ARMMMUIdx in_mmu_idx; ARMMMUIdx in_ptw_idx; + ARMSecuritySpace in_space; bool in_secure; bool in_debug; bool out_secure; bool out_rw; bool out_be; + ARMSecuritySpace out_space; hwaddr out_virt; hwaddr out_phys; void *out_host; @@ -218,6 +220,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t a= ttrs) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { + ARMSecuritySpace space =3D ptw->in_space; bool is_secure =3D ptw->in_secure; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx =3D ptw->in_ptw_idx; @@ -234,7 +237,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, if (regime_is_stage2(s2_mmu_idx)) { S1Translate s2ptw =3D { .in_mmu_idx =3D s2_mmu_idx, - .in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_P= hys_NS, + .in_ptw_idx =3D arm_space_to_phys(space), + .in_space =3D space, .in_secure =3D is_secure, .in_debug =3D true, }; @@ -292,10 +296,17 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, } =20 /* Check if page table walk is to secure or non-secure PA space. */ - ptw->out_secure =3D (is_secure - && !(pte_secure + if (is_secure) { + bool out_secure =3D !(pte_secure ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW)); + : env->cp15.vtcr_el2 & VTCR_NSW); + if (!out_secure) { + is_secure =3D false; + space =3D ARMSS_NonSecure; + } + } + ptw->out_secure =3D is_secure; + ptw->out_space =3D space; ptw->out_be =3D regime_translation_big_endian(env, mmu_idx); return true; =20 @@ -326,7 +337,10 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Transl= ate *ptw, } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -369,7 +383,10 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transl= ate *ptw, #endif } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -875,6 +892,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Transl= ate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } result->f.phys_addr =3D phys_addr; return false; @@ -1579,6 +1597,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ @@ -2363,6 +2382,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, */ if (sattrs.ns) { result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } else if (!secure) { /* * NS access to S memory must fault. @@ -2712,6 +2732,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool is_secure =3D ptw->in_secure; bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; + ARMSecuritySpace ipa_space, s2walk_space; bool is_el0; uint64_t hcr; =20 @@ -2724,20 +2745,24 @@ static bool get_phys_addr_twostage(CPUARMState *env= , S1Translate *ptw, =20 ipa =3D result->f.phys_addr; ipa_secure =3D result->f.attrs.secure; + ipa_space =3D result->f.attrs.space; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure =3D !(ipa_secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW); + s2walk_space =3D arm_secure_to_space(s2walk_secure); } else { assert(!ipa_secure); s2walk_secure =3D false; + s2walk_space =3D ipa_space; } =20 is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; - ptw->in_ptw_idx =3D s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; + ptw->in_space =3D s2walk_space; =20 /* * S1 is done, now do S2 translation. @@ -2825,11 +2850,12 @@ static bool get_phys_addr_with_struct(CPUARMState *= env, S1Translate *ptw, ARMMMUIdx s1_mmu_idx; =20 /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. + * The page table entries may downgrade Secure to NonSecure, but + * cannot upgrade a NonSecure translation regime's attributes + * to Secure or Realm. */ result->f.attrs.secure =3D is_secure; + result->f.attrs.space =3D ptw->in_space; =20 switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -2871,7 +2897,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, =20 default: /* Single stage and second stage uses physical for ptw. */ - ptw->in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(ptw->in_space); break; } =20 @@ -2946,6 +2972,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_secure =3D is_secure, + .in_space =3D arm_secure_to_space(is_secure), }; return get_phys_addr_with_struct(env, &ptw, address, access_type, result, fi); @@ -2955,7 +2982,10 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - bool is_secure; + S1Translate ptw =3D { + .in_mmu_idx =3D mmu_idx, + }; + ARMSecuritySpace ss; =20 switch (mmu_idx) { case ARMMMUIdx_E10_0: @@ -2968,30 +2998,55 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - is_secure =3D arm_is_secure_below_el3(env); + ss =3D arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: + /* + * For Secure EL2, we need this index to be NonSecure; + * otherwise this will already be NonSecure or Realm. + */ + ss =3D arm_security_space_below_el3(env); + if (ss =3D=3D ARMSS_Secure) { + ss =3D ARMSS_NonSecure; + } + break; case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: - is_secure =3D false; + ss =3D ARMSS_NonSecure; break; - case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: case ARMMMUIdx_MSUser: - is_secure =3D true; + ss =3D ARMSS_Secure; + break; + case ARMMMUIdx_E3: + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_rme, env_archcpu(env))) { + ss =3D ARMSS_Root; + } else { + ss =3D ARMSS_Secure; + } + break; + case ARMMMUIdx_Phys_Root: + ss =3D ARMSS_Root; + break; + case ARMMMUIdx_Phys_Realm: + ss =3D ARMSS_Realm; break; default: g_assert_not_reached(); } - return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - is_secure, result, fi); + + ptw.in_space =3D ss; + ptw.in_secure =3D arm_space_is_secure(ss); + return get_phys_addr_with_struct(env, &ptw, address, access_type, + result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -2999,9 +3054,11 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *c= s, vaddr addr, { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + ARMSecuritySpace ss =3D arm_security_space(env); S1Translate ptw =3D { .in_mmu_idx =3D arm_mmu_idx(env), - .in_secure =3D arm_is_secure(env), + .in_space =3D ss, + .in_secure =3D arm_space_is_secure(ss), .in_debug =3D true, }; GetPhysAddrResult res =3D {}; --=20 2.34.1