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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/30] target/arm: Constify ID_PFR1 on user emulation
Date: Thu, 16 Feb 2023 17:10:57 +0000
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From: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c62ed05c122..22670c20c00 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7021,6 +7021,7 @@ static void define_pmu_regs(ARMCPU *cpu)
}
}
=20
+#ifndef CONFIG_USER_ONLY
/*
* We don't know until after realize whether there's a GICv3
* attached, and that is what registers the gicv3 sysregs.
@@ -7038,7 +7039,6 @@ static uint64_t id_pfr1_read(CPUARMState *env, const =
ARMCPRegInfo *ri)
return pfr1;
}
=20
-#ifndef CONFIG_USER_ONLY
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu =3D env_archcpu(env);
@@ -7998,8 +7998,16 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D =
1,
.access =3D PL1_R, .type =3D ARM_CP_NO_RAW,
.accessfn =3D access_aa32_tid3,
+#ifdef CONFIG_USER_ONLY
+ .type =3D ARM_CP_CONST,
+ .resetvalue =3D cpu->isar.id_pfr1,
+#else
+ .type =3D ARM_CP_NO_RAW,
+ .accessfn =3D access_aa32_tid3,
.readfn =3D id_pfr1_read,
- .writefn =3D arm_cp_write_ignore },
+ .writefn =3D arm_cp_write_ignore
+#endif
+ },
{ .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH,
.opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D =
2,
.access =3D PL1_R, .type =3D ARM_CP_CONST,
--=20
2.34.1