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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/30] target/arm: Reduce
arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
Date: Thu, 16 Feb 2023 17:10:56 +0000
Message-Id: <20230216171123.2518285-4-peter.maydell@linaro.org>
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From: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
arm_v7m_mmu_idx_all() and arm_v7m_mmu_idx_for_secstate_and_priv()
are only used for system emulation in m_helper.c.
Move the definitions to avoid prototype forward declarations.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230206223502.25122-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 14 --------
target/arm/m_helper.c | 74 +++++++++++++++++++++---------------------
2 files changed, 37 insertions(+), 51 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e1e018da463..759b70c646f 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -597,20 +597,6 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_i=
dx)
=20
int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
=20
-/*
- * Return the MMU index for a v7M CPU with all relevant information
- * manually specified.
- */
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
- bool secstate, bool priv, bool negpri);
-
-/*
- * Return the MMU index for a v7M CPU in the specified security and
- * privilege state.
- */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
- bool secstate, bool priv);
-
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
=20
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 76239c9abe9..b4964dca8a8 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -157,6 +157,43 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *en=
v, bool secstate)
=20
#else /* !CONFIG_USER_ONLY */
=20
+static ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
+ bool secstate, bool priv, bool negpri)
+{
+ ARMMMUIdx mmu_idx =3D ARM_MMU_IDX_M;
+
+ if (priv) {
+ mmu_idx |=3D ARM_MMU_IDX_M_PRIV;
+ }
+
+ if (negpri) {
+ mmu_idx |=3D ARM_MMU_IDX_M_NEGPRI;
+ }
+
+ if (secstate) {
+ mmu_idx |=3D ARM_MMU_IDX_M_S;
+ }
+
+ return mmu_idx;
+}
+
+static ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
+ bool secstate, bool=
priv)
+{
+ bool negpri =3D armv7m_nvic_neg_prio_requested(env->nvic, secstate);
+
+ return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
+}
+
+/* Return the MMU index for a v7M CPU in the specified security state */
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
+{
+ bool priv =3D arm_v7m_is_handler_mode(env) ||
+ !(env->v7m.control[secstate] & 1);
+
+ return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
+}
+
/*
* What kind of stack write are we doing? This affects how exceptions
* generated during the stacking are treated.
@@ -2859,41 +2896,4 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t a=
ddr, uint32_t op)
return tt_resp;
}
=20
-ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
- bool secstate, bool priv, bool negpri)
-{
- ARMMMUIdx mmu_idx =3D ARM_MMU_IDX_M;
-
- if (priv) {
- mmu_idx |=3D ARM_MMU_IDX_M_PRIV;
- }
-
- if (negpri) {
- mmu_idx |=3D ARM_MMU_IDX_M_NEGPRI;
- }
-
- if (secstate) {
- mmu_idx |=3D ARM_MMU_IDX_M_S;
- }
-
- return mmu_idx;
-}
-
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
- bool secstate, bool priv)
-{
- bool negpri =3D armv7m_nvic_neg_prio_requested(env->nvic, secstate);
-
- return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
-}
-
-/* Return the MMU index for a v7M CPU in the specified security state */
-ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
-{
- bool priv =3D arm_v7m_is_handler_mode(env) ||
- !(env->v7m.control[secstate] & 1);
-
- return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
-}
-
#endif /* !CONFIG_USER_ONLY */
--=20
2.34.1