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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 1/5] hw/cpu: Extend CPUState::cluster_index documentation Date: Thu, 16 Feb 2023 15:23:34 +0100 Message-Id: <20230216142338.82982-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676557562230100007 Copy part of the description of commit f7b78602fd ("accel/tcg: Add cluster number to TCG TB hash") in tcg_cpu_init_cflags(), improving a bit CPUState::cluster_index documentation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- accel/tcg/tcg-accel-ops.c | 13 ++++++++++++- include/hw/core/cpu.h | 2 ++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 19cbf1db3a..654aeec04c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -44,7 +44,18 @@ =20 void tcg_cpu_init_cflags(CPUState *cpu, bool parallel) { - uint32_t cflags =3D cpu->cluster_index << CF_CLUSTER_SHIFT; + uint32_t cflags; + + /* + * Include the cluster number in the hash we use to look up TBs. + * This is important because a TB that is valid for one cluster at + * a given physical address and set of CPU flags is not necessarily + * valid for another: + * the two clusters may have different views of physical memory, or + * may have different CPU features (eg FPU present or absent). + */ + cflags =3D cpu->cluster_index << CF_CLUSTER_SHIFT; + cflags |=3D parallel ? CF_PARALLEL : 0; cflags |=3D icount_enabled() ? CF_USE_ICOUNT : 0; cpu->tcg_cflags =3D cflags; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2417597236..d427db0bc7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -272,6 +272,8 @@ struct qemu_work_item; * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will * be the same as the cluster-id property of the CPU object's TYPE_CPU_C= LUSTER * QOM parent. + * Under TCG this value is propagated to @tcg_cflags. + * See TranslationBlock::TCG CF_CLUSTER_MASK. * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. --=20 2.38.1 From nobody Sat May 18 13:36:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Thu, 16 Feb 2023 06:23:52 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Dapeng Mi , Sean Christopherson , Bin Meng , Zhuocheng Ding , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhenyu Wang , qemu-riscv@nongnu.org, Alistair Francis , Zhao Liu , "Edgar E. Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 2/5] hw/cpu/cluster: Only add CPU objects to CPU cluster Date: Thu, 16 Feb 2023 15:23:35 +0100 Message-Id: <20230216142338.82982-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676557562231100008 Do not recursively add CPU and all their children objects. Simply iterate on the cluster direct children, which must be of TYPE_CPU. Otherwise raise an error. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/cpu/cluster.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index bf3e27e945..b0cdf7d931 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -39,12 +39,19 @@ typedef struct CallbackData { static bool add_cpu_to_cluster(Object *obj, void *opaque, Error **errp) { CallbackData *cbdata =3D opaque; - CPUState *cpu =3D (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + CPUState *cpu; =20 - if (cpu) { - cpu->cluster_index =3D cbdata->cluster->cluster_id; - cbdata->cpu_count++; + cpu =3D (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + if (!cpu) { + error_setg(errp, "cluster %s can only accept CPU types (got %s)", + object_get_canonical_path(OBJECT(cbdata->cluster)), + object_get_typename(obj)); + return false; } + + cpu->cluster_index =3D cbdata->cluster->cluster_id; + cbdata->cpu_count++; + return true; } =20 @@ -63,8 +70,9 @@ static void cpu_cluster_realize(DeviceState *dev, Error *= *errp) return; } =20 - object_child_foreach_recursive(cluster_obj, add_cpu_to_cluster, - &cbdata, NULL); + if (!object_child_foreach(cluster_obj, add_cpu_to_cluster, &cbdata, er= rp)) { + return; + } =20 /* * A cluster with no CPUs is a bug in the board/SoC code that created = it; --=20 2.38.1 From nobody Sat May 18 13:36:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1676557549; cv=none; d=zohomail.com; s=zohoarc; b=amXwZtN062UGi0JWq8D69lKVKfZiyPd32uminkh5y3Z2eSxnOygEFPx5URinkaTZR2ZBW0jBHDn2fGbM0IA+lwT9bgdcgBlR/HU55oCjsCdG0NRFvaayydR9sNi06P7gpnSQa5lx4qbRwuoYlYx2lbcZH2h+0ezySUkzA2GeccY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676557549; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 3/5] hw/cpu/cluster: Restrict CPU cluster to a particular CPU type Date: Thu, 16 Feb 2023 15:23:36 +0100 Message-Id: <20230216142338.82982-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676557550145100001 CPU cluster id is used by TCG accelerator to "group" CPUs sharing the same ISA features, so TranslationBlock can be shared between the cluster (see commit f7b78602fd "accel/tcg: Add cluster number to TCG TB hash"). This mean we shouldn't mix different kind of CPUs into the same cluster. Enforce that by adding a 'cpu-type' property. The cluster's realize() method will check all children are of that 'cpu-type' class. If the property is not set, the first CPU added to a cluster sets its CPU type, and only that type fo CPU can be added. Example of error: qemu-system-aarch64: cluster /machine/soc/rpu-cluster can only accept cor= tex-r5f-arm-cpu CPUs (got cortex-a9-arm-cpu) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/cpu/cluster.c | 19 ++++++++++++++++--- include/hw/cpu/cluster.h | 1 + 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index b0cdf7d931..0d06944824 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -28,6 +28,7 @@ =20 static Property cpu_cluster_properties[] =3D { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), + DEFINE_PROP_STRING("cpu-type", CPUClusterState, cpu_type), DEFINE_PROP_END_OF_LIST() }; =20 @@ -41,11 +42,17 @@ static bool add_cpu_to_cluster(Object *obj, void *opaqu= e, Error **errp) CallbackData *cbdata =3D opaque; CPUState *cpu; =20 - cpu =3D (CPUState *)object_dynamic_cast(obj, TYPE_CPU); + if (cbdata->cluster->cpu_type =3D=3D NULL) { + /* If no 'cpu-type' property set, enforce it with the first CPU ad= ded */ + assert(object_dynamic_cast(obj, TYPE_CPU) !=3D NULL); + cbdata->cluster->cpu_type =3D g_strdup(object_get_typename(obj)); + } + + cpu =3D (CPUState *)object_dynamic_cast(obj, cbdata->cluster->cpu_type= ); if (!cpu) { - error_setg(errp, "cluster %s can only accept CPU types (got %s)", + error_setg(errp, "cluster %s can only accept %s CPUs (got %s)", object_get_canonical_path(OBJECT(cbdata->cluster)), - object_get_typename(obj)); + cbdata->cluster->cpu_type, object_get_typename(obj)); return false; } =20 @@ -69,6 +76,12 @@ static void cpu_cluster_realize(DeviceState *dev, Error = **errp) error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); return; } + if (cluster->cpu_type) { + if (object_class_is_abstract(object_class_by_name(cluster->cpu_typ= e))) { + error_setg(errp, "cpu-type must be a concrete class"); + return; + } + } =20 if (!object_child_foreach(cluster_obj, add_cpu_to_cluster, &cbdata, er= rp)) { return; diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 53fbf36af5..c9792d6f05 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -76,6 +76,7 @@ struct CPUClusterState { =20 /*< public >*/ uint32_t cluster_id; + char *cpu_type; }; =20 #endif --=20 2.38.1 From nobody Sat May 18 13:36:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1676557552; cv=none; d=zohomail.com; s=zohoarc; b=JED/nnQesCxH37umC8xMP4AqNU8gLknz4AcPu7tYd9WnZmpeD6je2c3fGlwD/N54ijdEijl+VIimWwSpaKjcywFbWlL/gPl/d3CduvDWqW/XJHuLb0nPpT3/x0B63KOUsHfXNu+CVlP+nc6KRiDn2nKp8zPWYGJNBbald9iQs6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1676557552; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pkUuoVsPO7rj7crjxhqsXkiJdIbOheCDQODQm6zJmAM=; b=aZcTBzLj98++pFXcHxz5JOMeurZeJvqXN3NpesbKE2VT9VpYacc4BUPoH/d6u37UKcGOCe/sFG+nRuTtEkeVG55N5ZVMTPW3gAZaw15G7HMOl3GBRCvKwSqJanqRiHGhBHf1PlDuA+SMtUiVOWAKk1vATR8/J64cw/XkHeLlnGo= ARC-Authentication-Results: i=1; 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Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 4/5] hw/arm: Restrict CPU clusters to the expected type Date: Thu, 16 Feb 2023 15:23:37 +0100 Message-Id: <20230216142338.82982-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676557554125100001 ARM SSE expects v7-M cores; the ZynqMP SoC expects Cortex-A53/R5F. Do not allow any other CPU type by setting the cluster 'cpu-type' property. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/armsse.c | 1 + hw/arm/xlnx-zynqmp.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 0202bad787..1132fdcbe2 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -715,6 +715,7 @@ static void armsse_init(Object *obj) name =3D g_strdup_printf("cluster%d", i); object_initialize_child(obj, name, &s->cluster[i], TYPE_CPU_CLUSTE= R); qdev_prop_set_uint32(DEVICE(&s->cluster[i]), "cluster-id", i); + qdev_prop_set_string(DEVICE(&s->cluster[i]), "cpu-type", TYPE_ARMV= 7M); g_free(name); =20 name =3D g_strdup_printf("armv7m%d", i); diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 335cfc417d..e45cf88625 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -224,6 +224,8 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, Xl= nxZynqMPState *s, object_initialize_child(OBJECT(s), "rpu-cluster", &s->rpu_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->rpu_cluster), "cluster-id", 1); + qdev_prop_set_string(DEVICE(&s->rpu_cluster), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-r5f")); =20 for (i =3D 0; i < num_rpus; i++) { const char *name; @@ -381,6 +383,8 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize_child(obj, "apu-cluster", &s->apu_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->apu_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->apu_cluster), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-a53")); =20 for (i =3D 0; i < num_apus; i++) { object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]", --=20 2.38.1 From nobody Sat May 18 13:36:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1676557559; cv=none; d=zohomail.com; s=zohoarc; b=HYDkokrQp2hjekGBJsTjm4oOK5aeucCwfLVl8rsQekVMwIGF4csC9oCflLTrXg40fZEMoIxbtVdy1jVIjqxqRpBjkiJBO17pgzxTF/wSbWe6PFeaaWY+T3KQtdIWpo+fIwiu+SMYa2zDMZg6JY9Z2q+CcaNjsM6iL9yxZ/UGAwI= ARC-Message-Signature: i=1; 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Thu, 16 Feb 2023 06:24:09 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Dapeng Mi , Sean Christopherson , Bin Meng , Zhuocheng Ding , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Zhenyu Wang , qemu-riscv@nongnu.org, Alistair Francis , Zhao Liu , "Edgar E. Iglesias" , Paolo Bonzini , Marcel Apfelbaum , Robert Hoo , Yanan Wang , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Like Xu , Alistair Francis , Zhao Liu , Eduardo Habkost Subject: [PATCH 5/5] hw/riscv: Restrict CPU clusters to the expected type Date: Thu, 16 Feb 2023 15:23:38 +0100 Message-Id: <20230216142338.82982-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230216142338.82982-1-philmd@linaro.org> References: <20230216142338.82982-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1676557560241100001 Microchip PolarFire SoC expects U51/U54 cores, the SiFive Freedom board: the E31/E51 and U34/U54. Do not allow any other CPU type by setting the cluster 'cpu-type' property. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/riscv/microchip_pfsoc.c | 4 ++++ hw/riscv/sifive_u.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 2b91e49561..658307fdfb 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -150,6 +150,8 @@ static void microchip_pfsoc_soc_instance_init(Object *o= bj) =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_E51); =20 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, TYPE_RISCV_HART_ARRAY); @@ -161,6 +163,8 @@ static void microchip_pfsoc_soc_instance_init(Object *o= bj) =20 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUS= TER); qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_U54); =20 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, TYPE_RISCV_HART_ARRAY); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d3ab7a9cda..d0535746ca 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -763,6 +763,7 @@ static void sifive_u_soc_instance_init(Object *obj) =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + qdev_prop_set_string(DEVICE(&s->e_cluster), "cpu-type", SIFIVE_E_CPU); =20 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, TYPE_RISCV_HART_ARRAY); @@ -813,6 +814,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) * CPU must exist and have been parented into the cluster before the * cluster is realized. */ + qdev_prop_set_string(DEVICE(&s->u_cluster), "cpu-type", s->cpu_type); qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); =20 --=20 2.38.1